MAX1122EGK Datasheet, PDF (13/17 Pages) Maxim Integrated Products – 1.8V, 10-Bit, 170Msps Analog-to-Digital Converter with LVDS Outputs for Wideband Applications

1.8V, 10-Bit, 170Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
Digital Outputs (D0P/N–D9P/N, DCLKP/N,
ORP/N) and Control Input T/B
The digital outputs D0P/N–D9P/N, DCLKP/N, and
ORP/N are LVDS compatible, and data on
D0P/N–D9P/N is presented in either binary or two’s
complement format (Table 1). The T/B control line is an
LVCMOS-compatible input, which allows the user to
select the desired output format. Pulling T/B low outputs
data in two’s complement and pulling it high presents
data in offset binary format on the 10-bit parallel bus.
T/B has an internal pulldown resistor and may be left
unconnected in applications using only two’s comple-
ment output format. All LVDS outputs provide a typical
voltage swing of 0.4V around a common-mode voltage
of approximately 1.2V, and must be terminated at the
far end of each transmission line pair (true and comple-
mentary) with 100Ω. The LVDS outputs are powered
from a separate power supply, which can be operated
between 1.7V and 1.9V.
The MAX1122 offers an additional differential output
pair (ORP, ORN) to flag out-of-range conditions, where
out of range is above positive or below negative full
scale. An out-of-range condition is identified with ORP
(ORN) transitioning high (low).
Note: Although differential LVDS reduces single-ended
transients to the supply and ground planes, capacitive
loading on the digital outputs should still be kept as low
as possible. Using LVDS buffers on the digital outputs
of the ADC when driving off-board may improve overall
performance and reduce system timing constraints.
ADC FULL-SCALE = REFT - REFB
REFT
REFB
REFERENCE-
SCALING
AMPLIFIER
G
REFERENCE
BUFFER
REFIO
1V
CONTROL LINE TO
DISABLE REFERENCE
BUFFER
REFADJ
0.1μF
13kΩ TO 1MΩ
13kΩ TO 1MΩ
AV_CC AV_CC/2
Figure 6. Circuit Suggestions to Adjust the ADC’s Full-Scale
Range
Applications Information
Full-Scale Range Adjustments Using the
Internal Bandgap Reference
The MAX1122 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, an exter-
nal resistor value ranging from 13kΩ to 1MΩ may be
added between REFADJ and AGND. A similar
approach can be taken to increase the ADCs full-scale
range. Adding a variable resistor, potentiometer, or pre-
V_CLK
0.1μF
SINGLE-ENDED
INPUT TERMINAL ^0.1μF
50Ω
510Ω
8
7
2
MC100LVEL16
3
6
510Ω
4 _0.01μF 5
VGND
0.1μF
150Ω
0.1μF
150Ω
INP
INN
Figure 7. Differential, AC-Coupled, PECL-Compatible Clock Input Configuration
AV_CC OV_CC
CLKN CLKP
MAX1122
D0P/N–D9P/N
10
AGND OGND
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