MAX1082 Datasheet, PDF (13/24 Pages) Maxim Integrated Products – 300ksps/400ksps, Single-Supply, 4-Channel, Serial 10-Bit ADCs with Internal Reference

Table 1. Channel Selection in Single-Ended Mode (SGL / DIF = 1)
SEL2
0
1
0
1
SEL1
0
0
1
1
SEL0
1
1
0
0
CH0
+
CH1
+
CH2
+
CH3
+
COM
–
–
–
–
Table 2. Channel Selection in Pseudo-Differential Mode (SGL / DIF = 0)
SEL2
SEL1
SEL0
CH0
CH1
CH2
CH3
0
0
1
+
–
0
1
0
+
–
1
0
1
–
+
1
1
0
–
+
Serial Clock
The external clock not only shifts data in and out, but it
also drives the analog-to-digital conversion steps.
SSTRB pulses high for one clock period after the last bit
of the control byte. Successive-approximation bit deci-
sions are made and appear at DOUT on each of the
next 12 SCLK falling edges, MSB first (Figure 5). SSTRB
and DOUT go into a high-impedance state when CS
goes high; after the next CS falling edge, SSTRB out-
puts a logic low. Figure 6 shows the detailed serial-inter-
face timings.
The conversion must complete in 120µs or less, or
droop on the sample-and-hold capacitors may degrade
conversion results.
Data Framing
The falling edge of CS does not start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V_DD1 and V_DD2
are applied.
OR
The first high bit clocked into DIN after bit B4 of a
conversion in progress is clocked onto the DOUT pin
(Figure 7).
Once a start bit has been recognized, the current conver-
sion may only be terminated by pulling SHDN low.
The fastest the MAX1082/MAX1083 can run with CS held
low between conversions is 16 clocks per conversion.
Figure 7 shows the serial-interface timing necessary to
perform a conversion every 16 SCLK cycles. If CS is tied
low and SCLK is continuous, guarantee a start bit by first
clocking in 16 zeros.
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1082/MAX1083 in normal operating mode, ready to
convert with SSTRB = low. After the power supplies sta-
bilize, the internal reset time is 10µs, and no conver-
sions should be performed during this phase. If CS is
low, the first logic 1 on DIN is interpreted as a start bit.
Until a conversion takes place, DOUT shifts out zeros.
Additionally, wait for the reference to stabilize when
using the internal reference.
Power Modes
Save power by placing the converter in one of two low-
current operating modes or in full power-down between
conversions. Select the power mode through bit 1 and
bit 0 of the DIN control byte (Tables 3 and 4), or force
the converter into hardware shutdown by driving SHDN
to GND.
The software power-down modes take effect after the
conversion is completed; SHDN overrides any software
power mode and immediately stops any conversion in
progress. In software power-down mode, the serial
interface remains active while waiting for a new control
byte to start conversion and switch to full-power mode.
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