MAX1070_09 Datasheet, PDF (13/18 Pages) Maxim Integrated Products – 1.5Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs

1.5Msps, Single-Supply, Low-Power,
True-Differential, 10-Bit ADCs
CNVST
1
SCLK
HIGH-Z
DOUT
8
9
16
D9 D8
D7 D6
D5
D4 D3 D2 D1 D0 S1 S0
HIGH-Z
Figure 12. SPI/MICROWIRE Serial-Interface Timing—Single Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
SCLK
1
14
16
1
DOUT
0
0
0
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
0
0
Figure 13. SPI/MICROWIRE Serial-Interface Timing—Continuous Conversion (CPOL = CPHA = 0), (CPOL = CPHA = 1)
CNVST
2
SCLK
HIGH-Z
DOUT
16
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 S0
HIGH-Z
Figure 14. QSPI Serial-Interface Timing—Single Conversion (CPOL = 1, CPHA = 1)
QSPI
Unlike SPI, which requires two 1-byte reads to acquire
the 10 bits of data from the ADC, QSPI allows the mini-
mum number of clock cycles necessary to clock in the
data. The MAX1070/MAX1071 require 16 clock cycles
from the µP to clock out the 10 bits of data. Figure 14
shows a transfer using CPOL = 1 and CPHA = 1. The
conversion result contains three zeros, followed by the
10 data bits, 2 sub-bits, and a trailing zero with the data
in MSB-first format.
DSP Interface to the TMS320C54_
The MAX1070/MAX1071 can be directly connected
to the TMS320C54_ family of DSPs from Texas
Instruments, Inc. Set the DSP to generate its own
clocks or use external clock signals. Use either the
standard or buffered serial port. Figure 15 shows the
simplest interface between the MAX1070/MAX1071 and
the TMS320C54_, where the transmit serial clock
(CLKX) drives the receive serial clock (CLKR) and
SCLK, and the transmit frame sync (FSX) drives the
receive frame sync (FSR) and CNVST.
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