DS1390_09 Datasheet, PDF (13/26 Pages) Maxim Integrated Products – Low-Voltage SPI/3-Wire RTCs with Trickle Charger

Low-Voltage SPI/3-Wire RTCs with
Trickle Charger
Power Control
The power-control function is provided by a precise,
temperature-compensated voltage reference and a
comparator circuit that monitors the V_CC level. The
device is fully accessible and data can be written and
read when V_CC is greater than V_PF. However, when
V_CC falls below V_PF, the internal clock registers are
blocked from any access. If V_PF is less than V_BACKUP,
the device power is switched from V_CC to V_BACKUP
when V_CC drops below V_PF. If V_PF is greater than
V_BACKUP, the device power is switched from V_CC to
V_BACKUP when V_CC drops below V_BACKUP.
Timekeeping operation and register data are main-
tained from the V_BACKUP source until V_CC is returned to
nominal levels (Table 1). After V_CC returns above V_PF,
read and write access is allowed after RST goes high
(Figure 5).
Table 1. Power Control
SUPPLY
CONDITION
V_CC < V_PF,
V_CC < V_BACKUP
V_CC < V_PF,
V_CC > V_BACKUP
V_CC > V_PF,
V_CC < V_BACKUP
V_CC > V_PF,
V_CC > V_BACKUP
READ/WRITE
ACCESS)
No
No
Yes
Yes
POWERED BY
V_BACKUP
V_CC
V_CC
V_CC
Oscillator Circuit
All five devices use an external 32.768kHz crystal. The
oscillator circuit does not require any external resistors
or capacitors to operate. Table 2 specifies several crys-
tal parameters for the external crystal. If a crystal is
used with the specified characteristics, the startup time
is usually less than one second.
Table 2. Crystal Specifications*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nominal Frequency
f_O
32.768
kHz
Series Resistance
ESR
55
kΩ
Load Capacitance
C_L
6
pF
*The crystal, traces, and crystal input pins should be isolated
from RF generating signals. Refer to Application Note 58:
Crystal Considerations for Maxim Real-Time Clocks for addi-
tional specifications.
Clock Accuracy
The accuracy of the clock is dependent upon the accu-
racy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and
the capacitive load for which the crystal was trimmed.
Additional error is added by crystal frequency drift
caused by temperature shifts. External circuit noise
coupled into the oscillator circuit can result in the clock
running fast. Figure 7 shows a typical PC board layout
for isolation of the crystal and oscillator from noise.
Refer to Application Note 58: Crystal Considerations
with Maxim Real-Time Clocks for detailed information.
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
NOTE: AVOID ROUTING SIGNAL LINES
IN THE CROSSHATCHED AREA
(UPPER LEFT QUADRANT) OF
THE PACKAGE UNLESS THERE IS
GND
A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE DEVICE PACKAGE.
Figure 7. Layout Example
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