MAX9450 Datasheet, PDF (12/17 Pages) Maxim Integrated Products – High-Precision Clock Generators with Integrated VCXO

High-Precision Clock Generators
with Integrated VCXO
A
B
C
D
EF
G
t_LOW t_HIGH
SMBCLK
H
I JK
LM
SMBDATA
t_SU:STA tHD:STA
A = START CONDITION
B = MSB OF ADDRESS CLOCKED INTO SLAVE
C = LSB OF ADDRESS CLOCKED INTO SLAVE
D = R/W BIT CLOCKED INTO SLAVE
E = SLAVE PULLS SMBDATA LINE LOW
t_SU:DAT
t_HD:DAT
F = ACKNOWLEDGE BIT CLOCKED INTO MASTER
G = MSB OF DATA CLOCKED INTO MASTER
H = LSB OF DATA CLOCKED INTO MASTER
I = MASTER PULLS DATA LINE LOW
t_SU:STO t_BUF
J = ACKNOWLEDGE CLOCKED INTO SLAVE
K = ACKNOWLEDGE CLOCK PULSE
L = STOP CONDITION
M = NEW START CONDITION
Figure 6. SMBus Read Timing Diagram
SPI Interface
The SPI interface is activated when AD0 = AD1 = high.
The SPI port is a write-only interface, and it uses the
three inputs: CS, SCL, and SDA. Bit D15 is always zero,
indicating the write-only mode, as shown in Figure 5.
D14–D8 are the register address bits and D7–D0 are
the data bits. In Table 4, the register address mapping
is still valid, except the first address bit on the left is not
used. D14 is the MSB of the address, and D7 is the
MSB of the data. D15–D0 are sent with MSB (D15) first.
The maximum SCL frequency is 2MHz.
To perform a write, set D15 = 0, drive CS low, toggle
SCL to latch SDA data on the rising edge, then drive
CS high after 16 SCL cycles for two SCL cycles to sig-
nal the boundary of a 16-bit word (Figure 5). SCL must
be low when CS falls at the start of a transmission.
Switching of SCL and SDA is ignored unless CS is low.
Figure 7 shows the SPI write operation timing diagram
and Figure 8 shows SPI register address and data con-
figuration function setting tables.
CS
SCLK
DIN
t_CSS
t_DS
t_DS
D15
D14
t_CSW
t_CSH
f_SCL
D1
D0
Figure 7. SPI Write Operation Timing Diagram
CS
SLK
SDA
D15 D14
D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
REGISTER ADDRESS
REGISTER DATA
Figure 8. SPI Register Address and Data Configuration Function Setting Tables
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