MAX5175 Datasheet, PDF (12/16 Pages) Maxim Integrated Products – Low-Power, Serial, 12-Bit DACs with Force/Sense Voltage Output

Low-Power, Serial, 12-Bit DACs with
Force/Sense Voltage Output
CS
SCLK
DIN
1
8
C2 C1 C0 D9 D8 D7 D6 D5
9
16
D4 D3 D2 D1 D0 S2 S1 S0
COMMAND
EXECUTED
Figure 4. Serial-Interface Timing Diagram
CS
SCLK
DIN
DOUT
t_CSO
t_CSS
t_CSH
t_CH
t_CL
t_CP
t_DS
t_D01
t_D02
t_CSW
t_CS1
t_DH
Figure 5. Detailed Serial-Interface Timing Diagram
Serial-Data Output (DOUT)
The serial-data output (DOUT) is the internal shift regis-
ter’s output and allows for daisy-chaining of multiple
devices as well as data readback (see Applications
Information). By default upon start-up, data shifts out of
DOUT on the serial clock’s rising edge (Mode 0) and
provides a lag of 16 clock cycles, thus maintaining SPI,
QSPI, and MICROWIRE compatibility. However, if the
device is programmed for Mode 1, then the output data
lags DIN by 16.5 clock cycles and is clocked out on the
serial clock’s rising edge. During shutdown, DOUT
retains its last digital state prior to shutdown.
User-Programmable Logic Output (UPO)
The UPO allows control of an external device through
the serial interface, thereby reducing the number of
microcontroller I/O pins required. During power-down,
this output will retain its digital state prior to shutdown.
When CLR is pulled low, UPO will reset to its pro-
grammed default state. See Table 1 for specific com-
mands to control the UPO.
Reset (RS) and Clear (CLR)
The MAX5175/MAX5177 offers a clear pin (CLR) which
resets the output voltage. If RST = DGND, then CLR
resets the output voltage to the minimum voltage (0 if
no offset is introduced). If RST = V_DD, then CLR resets
the output voltage to midscale. In either case, CLR will
reset UPO to its programmed default state.
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