MAX1559 Datasheet, PDF (12/14 Pages) Maxim Integrated Products – 5-Output Power-Management IC For Low-Cost PDAs

5-Output Power-Management IC For
Low-Cost PDAs
where V_DD is the I/O voltage of the PWM output. The
Thevenin impedance is the sum of resistors R_W and R_D:
R_THEV = R_D+ R_W
The output voltage (V_OUT) as a function of the PWM
average voltage (V_THEV) is:
V_OUT
=
V_REF
×
₁₊
R₁
R₂


+
(V_REF
− V_THEV
R_THEV
)
×
R₁
When using the PWM adjustment method, R_D isolates
the capacitor from the feedback loop of the MAX1559.
The cutoff frequency of the lowpass filter is defined as:
f_C
=
2
×
π
1
× R_THEV
The cutoff frequency should be at least 2 decades
below the PWM frequency to minimize the induced AC
ripple at the output.
An important consideration is the turn-on transient cre-
ated by the initial charge on the filter capacitor C10.
This capacitor forms a time constant with R_THEV, which
causes the output to initialize at a higher than intended
voltage. This overshoot can be minimized by scaling
R_D as high as possible compared to R1 and R2.
Alternately, the µP can briefly keep the LCD disabled
until the PWM voltage has had time to stabilize.
PC Board Layout and Grounding
Careful PC board layout is important for minimizing
ground bounce and noise. Keep the MAX1559’s
ground pin and the ground leads of the input and out-
put capacitors less than 0.2in (5mm) apart. In addition,
keep all connections to FB and LX as short as possible.
In particular, external feedback resistors should be as
close to FB as possible. To minimize output voltage rip-
ple and to maximize output power and efficiency, use a
ground plane and solder GND directly to the ground
plane. Refer to the MAX1559 evaluation kit for a layout
example.
V_IN
3.3V
MAIN
1V
COR1
3.3V ACTIVATED
WHEN V_IN RISES
TO 3.6V
3.3V DEACTIVATED
WHEN V_IN FALLS
TO 3.0V
COR1 NOT ACTIVATED
UNTIL 3.3V IN REGULATION
COR1 DEACTIVATED AND
RS LOW WHEN MAIN
FALLS TO 3V
RS
OUTPUT
RS EXTERNAL RC SET FOR
10ms DELAY FROM 1V GOOD
Figure 3. RS and Power-On, Power-Off Timing for 3.3V and 1V
Core
Thermal Considerations
In most applications, the circuit is located on a multilay-
er board and full use of the four or more layers is rec-
ommended. For heat dissipation, connect the exposed
backside pad of the QFN package to a large analog
ground plane, preferably on a surface of the board that
receives good airflow. Typical applications use multiple
ground planes to minimize thermal resistance. Avoid
large AC currents through the analog ground plane.
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