MAX15034 Datasheet, PDF (12/25 Pages) Maxim Integrated Products – Configurable, Single-/Dual-Output, Synchronous Buck Controller for High-Current Applications

Configurable, Single-/Dual-Output, Synchronous
Buck Controller for High-Current Applications
Dual-Output/Dual-Phase Select (MODE)
The MAX15034 can operate as a dual-output, indepen-
dently regulated buck converter, or as a dual-phase,
single-output buck converter. The MODE input selects
between the two operating modes. When MODE is
grounded (logic-low), VEA1 and VEA2 connect to CEA1
and CEA2, respectively (see Figure 1), and the device
operates as a two-output DC-DC converter. When
MODE is connected to REG (logic-high), VEA2 is dis-
connected and VEA1 is routed to both CEA1 and CEA2
and the device works as a dual-phase, single-output
buck regulator with each output 180° out of phase with
respect to each other.
Supply Voltage Connections (V_IN/V_REG)
The MAX15034 accepts a wide input voltage range at
IN of 5V to 28V. An internal linear regulator steps down
V_IN to 5.1V (typ) and provides power to the MAX15034.
The output of this regulator is available at REG. For V_IN
= 4.75V to 5.5V, connect IN and REG together external-
ly. REG can supply up to 65mA for external loads.
Bypass REG to AGND with a 4.7μF ceramic capacitor
for high-frequency noise rejection and stable operation.
REG supplies the current for the MAX15034’s internal
circuitry and for the MOSFET gate drivers (when con-
nected externally to V_DD), and can source up to 65mA.
Calculate the maximum bias current (I_BIAS) for the
MAX15034:
( ) I_BIAS = I_IN + f_SW × Q_GQ1 + Q_GQ2 + Q_GQ3 + Q_GQ4
where I_IN is the quiescent supply current into IN (4mA,
typ), Q_GQ1, Q_GQ2, Q_GQ3, Q_GQ4 are the total gate
charges of MOSFETs Q1 through Q4 at V_GS = 5V (see
Figure 6), and f_SW is the switching frequency of each
individual phase.
Low-Side MOSFET Driver Supply (V_DD)
V_DD is the power input for the low-side MOSFET dri-
vers. Connect the regulator output REG externally to
V_DD through an R-C lowpass filter. Use a 1Ω resistor
and a parallel combination of 1μF and 0.1μF ceramic
capacitors to filter out the high peak currents of the
MOSFET drivers from the sensitive internal circuitry.
High-Side MOSFET Drive Supply (BST_)
BST1 and BST2 supply the power for the high-side
MOSFET drivers for output 1 and output 2, respectively.
Connect BST1 and BST2 to V_DD through rectifier
diodes D1 and D2 (see Figure 6). Connect a 0.1μF
ceramic capacitor between BST_ and LX_.
Minimize the trace inductance from BST_ and V_DD to
the rectifier diodes, D1 and D2, and from BST_ and LX_
to the boost capacitors, C8 and C9 (see Figure 6). This
is accomplished by using short, wide trace lengths.
Undervoltage Lockout (UVLO)/
Power-On Reset (POR)/Soft-Start
The MAX15034 includes an undervoltage lockout
(UVLO) with hysteresis, and a power-on reset circuit for
converter turn-on and monotonic rise of the output volt-
age. The UVLO threshold monitors V_REG and is inter-
nally set between 4.0V and 4.5V with 200mV of
hysteresis. Hysteresis eliminates chattering during
startup. Most of the internal circuitry, including the
oscillator, turns on when V_REG reaches 4.5V. The
MAX15034 draws up to 4mA (typ) of current before
V_REG reaches the UVLO threshold.
The compensation network at the current-error ampli-
fiers (CLP1 and CLP2) provides an inherent soft-start of
the output voltage. It includes (R14 and C10) in parallel
with C11 at CLP1 and (R15 and C12) in parallel with
C13 at CLP2 (see Figure 6). The voltage at the current-
error amplifier output limits the maximum current avail-
able to charge the output capacitors. The capacitor at
CLP_ in conjunction with the finite output-drive current
of the current-error amplifier yields a finite rise time for
the output current and thus, the output voltage.
Setting the Switching Frequency (f_SW)
An internal oscillator generates the 180^o out-of-phase
clock signals required for both PWM modulators. The
oscillator also generates the 2V_P-P voltage ramps nec-
essary for the PWM comparators. The oscillator fre-
quency can be set from 200kHz to 2MHz by an external
resistor (R_T) connected from RT/CLKIN to AGND (see
Figure 6). The equation below shows the relationship
between R_T and the switching frequency:
f_OSC
=
2.5 × 10¹⁰
R_RT
Hz
where R_RT is in ohms and the per-phase switching fre-
quency is f_SW = f_OSC/2.
Use RT/CLKIN as a clock input to synchronize the
MAX15034 to an external frequency (f_RT/CLKIN).
Applying an external clock to RT/CLKIN allows each
PWM section to work at a frequency equal to
f_RT/CLKIN/2. An internal comparator with a 1.6V thresh-
old detects f_RT/CLKIN. If f_RT/CLKIN is present, internal
logic switches from the internal oscillator clock, to the
clock present at RT/CLKIN.
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