MAX1473_11 Datasheet, PDF (12/15 Pages) Maxim Integrated Products – 315MHz/433MHz ASK Superheterodyne Receiver with Extended Dynamic Range

315MHz/433MHz ASK Superheterodyne
Receiver with Extended Dynamic Range
MAX1473
DATA
SLICER
DATA
SLICER
MAX1473
25
DATAOUT
20
23
19
DSN
DSP
DFO
C4
R1
25
DATAOUT
R1
23
20
19
DSP
DSN
R4
DFO
R3
Figure 2. Generating Data Slicer Threshold
Note that a long string of zeros or 1’s can cause the
threshold to drift. This configuration works best if a cod-
ing scheme, such as Manchester coding, which has an
equal number of zeros and 1’s, is used.
To prevent continuous toggling of DATAOUT in the
absence of an RF signal due to noise, hysteresis can
be added to the data slicer as shown in Figure 3.
Peak Detector
The peak detector output (PDOUT), in conjunction with
an external RC filter, creates a DC output voltage equal
to the peak value of the data signal. The resistor pro-
vides a path for the capacitor to discharge, allowing the
peak detector to dynamically follow peak changes of
the data filter output voltage. For faster receiver startup,
the circuit shown in Figure 4 can be used.
Layout Considerations
A properly designed PCB is an essential part of any
RF/microwave circuit. On high-frequency inputs and
outputs, use controlled-impedance lines and keep
them as short as possible to minimize losses and radia-
tion. At high frequencies, trace lengths that are on the
order of λ/10 or longer act as antennas.
Keeping the traces short also reduces parasitic induc-
tance. Generally, 1in of a PCB trace adds about 20nH
of parasitic inductance. The parasitic inductance can
have a dramatic effect on the effective inductance of a
passive component. For example, a 0.5in trace con-
necting a 100nH inductor adds an extra 10nH of induc-
tance or 10%.
To reduce the parasitic inductance, use wider traces
and a solid ground or power plane below the signal
traces. Also, use low-inductance connections to ground
on all GND pins, and place decoupling capacitors
close to all power-supply pins.
R2 *OPTIONAL
C4
Figure 3. Generating Data Slicer Hysteresis
MAX1473
DATA
SLICER
25
DATAOUT
20
23 19
DSN
DSP DFO
25kΩ
47nF
26
PDOUT
Figure 4. Using PDOUT for Faster Startup
PROCESS: CMOS
Chip Information
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