MAX14611_14 Datasheet, PDF (12/15 Pages) Maxim Integrated Products – Quad Bidirectional Low-Voltage Quad Bidirectional Low-Voltage

MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Rise-Time Accelerators (Figure 5)
The device has internal rise-time accelerators, allowing
operation up to 20Mbps. The rise-time accelerators are
present on both sides of the device and act to speed
up the rise time of the input and output of the device,
regardless of the direction of the data. The triggering
mechanism for these accelerators is both level and edge
sensitive. To prevent false triggering of the rise-time
accelerators, and to take full advantage of them, signal
rise/fall times of less than 2ns/V are recommended for
both sides of the device. In open-drain driving, the rec-
ommendation only applies for fall time. Under less noisy
conditions, longer signal fall times can be acceptable.
Three-State Output Mode (TS)
Drive TS low to place the device in three-state output
mode. Connect TS to V_L (logic-high) for normal opera-
tion. Activating the three-state output mode disconnects
the internal 10kI pullup resistors on the I/OVCC_ and
I/OVL_ lines. This forces the I/O lines to a high-impedance
state and decreases the supply current to less than 1FA.
The high-impedance I/O lines in three-state output mode
allow for use in a multidrop network. When in three-state
output mode, keep the I/OVL_ voltage below (V_L + 0.3V),
and keep the I/OVCC_ voltage below (V_CC + 0.3V).
Thermal Short-Circuit Protection
Thermal-overload detection protects the device from
short-circuit fault conditions. In the event of a short-circuit
fault and when the junction temperature (T_J) reaches
+150NC (typ), a thermal sensor signals the three-state
output mode logic to force the device into three-state out-
put mode. When T_J has cooled to +130NC (typ), normal
operation resumes.
High ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
The I/OVCC_ lines have extra protection against static
electricity. Maxim’s engineers have developed state-of-
the-art structures to protect these pins against ESD of
±6kV without damage.
The ESD structures withstand high ESD in all states:
normal operation, three-state output mode, and powered
down. After an ESD event, the device keeps working
without latchup, whereas competing products can latch
and must be powered down to remove latchup. ESD pro-
tection can be tested in various ways. The I/OVCC_ lines
of this product family are characterized for protection.to
±6kV using the Human Body Model.
ESD Test Conditions
Contact Maxim for a reliability report that documents test
setup, test methodology, and test results.
Applications Information
Power-Supply Decoupling
Bypass V_L to ground with a 0.1FF capacitor to reduce
ripple and ensure correct data transmission. See the
Typical Operating Circuit. To ensure full Q6kV ESD
protection, bypass V_CC to ground with a 1FF capacitor.
Place all capacitors as close as possible to the power-
supply pins (V_CC a­ nd V_­L).
Push-Pull vs. Open-Drain Driving
The device can be driven in a push-pull configuration.
The device includes internal 10kI resistors that pull
up I/OVL_ and I/OVCC_ to their respective power sup-
plies, allowing operation of the I/O lines with open-drain
devices. See the Timing Characteristics table for maxi-
mum data rates when using open-drain drivers (Figure 1,
Figure 2, Figure 3, Figure 4).
Maxim Integrated
  12