MAX13485E Datasheet, PDF (12/16 Pages) Maxim Integrated Products – Half-Duplex RS-485/RS-422 Transceivers in uDFN

Half-Duplex RS-485/RS-422 Transceivers in µDFN
Detailed Description
The MAX13485E/MAX13486E half-duplex, high-speed
transceivers for RS-485/RS-422 communication contain
one driver and one receiver. These devices feature fail-
safe circuitry that guarantees a logic-high receiver out-
put when receiver inputs are open or shorted, or when
they are connected to a terminated transmission line
with all drivers disabled (see the Fail-Safe section). The
MAX13485E/MAX13486E also feature a hot-swap capa-
bility allowing line insertion without erroneous data
transfer (see the Hot-Swap Capability section). The
MAX13485E features reduced slew-rate drivers that
minimize EMI and reduce reflections caused by
improperly terminated cables, allowing error-free trans-
mission up to 500kbps. The MAX13486E driver slew
rate is not limited, making transmit speeds up to
16Mbps possible.
Fail-Safe
The MAX13485E/MAX13486E guarantee a logic-high
receiver output when the receiver inputs are shorted or
open, or when they are connected to a terminated
transmission line with all drivers disabled. This is done by
setting the receiver input threshold between -50mV and
-200mV. If the differential receiver input voltage (A - B) is
greater than or equal to -50mV, RO is logic-high. If (A - B)
is less than or equal to -200mV, RO is logic-low. In the
case of a terminated bus with all transmitters disabled,
the receiver’s differential input voltage is pulled to 0V by
the termination. With the receiver thresholds of the
MAX13485E/MAX13486E, this results is a logic-high with
a 50mV minimum noise margin. Unlike previous fail-safe
devices, the -50mV to -200mV threshold complies with
the ±200mV EIA/TIA-485 standard.
Hot-Swap Capability
Hot-Swap Inputs
When circuit boards are inserted into a hot or powered
backplane, differential disturbances to the data bus
can lead to data errors. Upon initial circuit-board inser-
tion, the data communication processor undergoes its
own power-up sequence. During this period, the
processor’s logic-output drivers are high impedance
and are unable to drive the DE and RE inputs of these
devices to a defined logic level. Leakage currents up to
±10µA from the high impedance state of the proces-
sor’s logic drivers could cause standard CMOS enable
inputs of a transceiver to drift to an incorrect logic level.
Additionally, parasitic circuit-board capacitance could
cause coupling of V_CC or GND to the enable inputs.
Without the hot-swap capability, these factors could
improperly enable the transceiver’s driver or receiver.
V_CC
TIMER
TIMER
10µs
SR LATCH
5kΩ
DE
100µA
500µA
M1
M2
DE
(HOT SWAP)
Figure 9. Simplified Structure of the Driver Enable Pin (DE)
When V_CC rises, an internal pulldown circuit holds DE
low and RE high. After the initial power-up sequence,
the pulldown circuit becomes transparent, resetting the
hot-swap tolerable input.
Hot-Swap Input Circuitry
The enable inputs feature hot-swap capability. At the
input there are two nMOS devices, M1 and M2 (Figure
9). When V_CC ramps from zero, an internal 7µs timer
turns on M2 and sets the SR latch, which also turns on
M1. Transistors M2, a 1.5mA current sink, and M1, a
500µA current sink, pull DE to GND through a 5kΩ
resistor. M2 is designed to pull DE to the disabled state
against an external parasitic capacitance up to 100pF
that can drive DE high. After 7µs, the timer deactivates
M2 while M1 remains on, holding DE low against tri-
state leakages that can drive DE high. M1 remains on
until an external source overcomes the required input
current. At this time, the SR latch resets and M1 turns
off. When M1 turns off, DE reverts to a standard high-
impedance CMOS input. Whenever V_CC drops below
1V, the hot-swap input is reset.
For RE there is a complementary circuit employing two
pMOS devices pulling RE to V_CC.
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