MAX1286 Datasheet, PDF (12/15 Pages) Maxim Integrated Products – 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23

150ksps, 12-Bit, 2-Channel Single-Ended, and
1-Channel True-Differential ADCs in SOT23
CNVST
1ST BYTE READ
1
4
8
SCLK
2ND BYTE READ
12
16
DOUT
B11
MSB
B10
B9
B8
B7
B6 B5
B4
B3 B2
B1
B0
LSB
HIGH-Z
SAMPLING INSTANT
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
CS
SCK
MISO
V_DD
QSPI
SS
CNVST
SCLK
DOUT
MAX1286–
MAX1289
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
High-frequency noise in the power supply (V_DD) may
degrade the performance of the ADC’s fast comparator.
Bypass V_DD to the star ground with a 0.1µF capacitor,
located as close as possible to the MAX1286–MAX1289s’
power-supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5Ω) if
the power supply is extremely noisy.
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
CONTROL BIT
MAX1286–MAX1289
SETTINGS
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
SMP
CKE
D/A
P
S
R/W
UA
BF
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data
output time.
1
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial
clock.
X
Data Address Bit
X
Stop Bit
X
Start Bit
X
Read/Write Bit Information
X
Update Address
X
Buffer Full Status Bit
12 ______________________________________________________________________________________