MAX11329_V1 Datasheet, PDF (12/37 Pages) Maxim Integrated Products – 3Msps, 12-/10-Bit, 8-/16-Channel ADCs with Post-Mux External Signal Conditioning Access

MAX11329–MAX11332
3Msps, 12-/10-Bit, 8-/16-Channel ADCs with
Post-Mux External Signal Conditioning Access
Pin Description (continued)
MAX11329
MAX11331
(16 CHANNEL)
MAX11330
MAX11332
(8 CHANNEL)
20, 21
20, 21
22
22
23
23
24
24
25
25
26
26
27
27
28
28
—
—
NAME
FUNCTION
V_DD
SCLK
CS
DIN
DGND
OVDD
DOUT
EOC
EP
Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF
capacitors.
Serial Clock Input. Clocks data in and out of the serial interface.
Active-Low Chip Select Input. When CS is low, the serial interface is enabled.
When CS is high, DOUT is high impedance or three-state.
Serial Data Input. DIN data is latched into the serial interface on the rising edge
of SCLK.
Digital I/O Ground
Digital Power-Supply Input. Bypass to GND with a 10FF in parallel with a 0.1FF
capacitors.
Serial Data Output. Data is clocked out on the falling edge of SCLK. When CS is
high, DOUT is high impedance or three-state.
End of Conversion Output. Data is valid after EOC is driven low (internal clock mode
only).
Exposed Pad. Connect EP directly to GND plane for guaranteed performance.
  12