MAX1069 Datasheet, PDF (12/20 Pages) Maxim Integrated Products – 58.6ksps, 14-Bit, 2-Wire Serial ADC

58.6ksps, 14-Bit, 2-Wire Serial ADC
in a 14-Pin TSSOP
CONTROL
LOGIC
AV_DD ⁸
AGND ⁹
AIN ¹⁰
11
T/H
AGNDS
+4.096V
5kΩ
REFERENCE
REFADJ ¹²
13
REF
Figure 3. MAX1069 Simplified Functional Diagram
4MHz
INTERNAL
OSCILLATOR
6 _ADD0
5 _ADD1
4 _ADD2
14 _ADD3
3 _SDA
2 _SCL
7 _DVDD
1 _DGND
CLOCK
IN
SAR
ADC
OUT
REF
A_V = 1.0
OUTPUT SHIFT
REGISTER
MAX1069
5.0V
0.1µF
10µF
0.1µF
8 _{AVDDMAX1069 DVDD 7}
ADD0 ⁶
ADD1 ⁵
13 _REF
ADD2 ⁴
12 _REFADJ
SDA ³
SCL ²
3.0V
0.1µF
R_P
µC
V_DD
R_P
SDA
SCL
ANALOG 10 _AIN
SOURCE
11 _AGNDS
ADD3 ¹⁴
V_SS
AGND DGND
9
1
I²C ADDRESS IS 0110111
Figure 4. Typical Application Circuit
forming a digital representation of the analog input sig-
nal. During the conversion period, the MAX1069 holds
SCL low (clock stretching).
The time required for the T/H to acquire an input signal
is a function of the analog input source impedance. If
the input signal source impedance is high, lengthen the
acquisition time by reducing f_SCL. The MAX1069 pro-
vides two SCL cycles (t_ACQ), in which the track-and-
hold capacitance must acquire a charge representing
the input signal. Minimize the input source impedance
(R_SOURCE) to allow the track-and-hold capacitance to
charge within the allotted time. R_SOURCE should be
less than 12.9kΩ for f_SCL = 400kHz and less than 2.4kΩ
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