DS3102_08 Datasheet, PDF (119/141 Pages) Maxim Integrated Products – Stratum 3 Timing Card IC with Synchronous Ethernet Support

____________________________________________________________________________________________ DS3102
Register Name:
Register Description:
Register Address:
FSCR1
Frame-Sync Configuration Register 1
7Ah
Bit #
Name
Default
7
2K8KSRC
0
6
5
4
SYNCSRC[2:0]
0
0
0
3
8KINV
0
2
8KPUL
0
1
2KINV
0
0
2KPUL
0
Bit 7: 2kHz/8kHz Source (2K8KSRC). This configuration bit specifies the source for the 2kHz and 8kHz outputs
available on clock outputs. When MCR4:LKT4T0 = 1 it is always connected to the T0 DPLL. See Section 7.8.2.3.
0 = T0 DPLL
1 = T4 DPLL
Bits 6 to 4: SYNC12 Source (SYNCSRC[2:0]). When external frame sync is configured for SYNC123 mode, this
field specifies the input clocks to associate with the SYNC1 and SYNC2 pins. SYNC3 is always associated with
input clock IC9 in this mode. See Section 7.9.2.1.
0XX = SYNC1 pin associated with IC3 or IC5, SYNC2 pin associated with IC4 or IC6, SYC3 pin associated
with IC9 or IC2
1X0 = SYNC1 pin associated with IC3, SYNC2 pin associated with IC4
1X1 = SYNC1 pin associated with IC5, SYNC2 pin associated with IC6
10X = SYNC3 pin associated with IC9
11X = SYNC3 pin associated with IC2
Bit 3: 8kHz Invert (8KINV). When this bit is set to 1 the 8kHz signal on clock output FSYNC is inverted. See
Section 7.8.2.4.
0 = FSYNC not inverted
1 = FSYNC inverted
Bit 2: 8kHz Pulse (8KPUL). When this bit is set to 1, the 8kHz signal on clock output FSYNC is pulsed rather than
50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of FSYNC is equal to the
clock period of OC3. See Section 7.8.2.4.
0 = FSYNC not pulsed; 50% duty cycle
1 = FSYNC pulsed, with pulse width equal to OC3 period
Bit 1: 2kHz Invert (2KINV). When this bit is set to 1 the 2kHz signal on clock output MFSYNC is inverted. See
Section 7.8.2.4.
0 = MFSYNC not inverted
1 = MFSYNC inverted
Bit 0: 2kHz Pulse (2KPUL). When this bit is set to 1, the 2kHz signal on clock output MFSYNC is pulsed rather
than 50% duty cycle. In this mode output clock OC3 must be enabled, and the pulse width of MFSYNC is equal to
the clock period of OC3. See Section 7.8.2.4.
0 = MFSYNC not pulsed; 50% duty cycle
1 = MFSYNC pulsed, with pulse width equal to OC3 period
Rev: 102808
119 of 141