MAX7370 Datasheet, PDF(11/37 Page) Maxim Integrated Products – 8 x 8 Key-Switch Controller and LED Driver/GPIOs with I2C Interface and High Level of ESD Protection

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MAX7370

8 x 8 Key-Switch Controller and LED Driver/GPIOs

with I2C Interface and High Level of ESD Protection

the frequency at which the key-repeat code is entered

into the FIFO thereafter. The key being pressed is not

entered again into the FIFO. Bit D7 specifies whether

the autorepeat function is enabled with 0, denoting

autorepeat disabled, and 1, denoting autorepeat

enabled. Bits D[3:0] specify the autorepeat delay in

terms of debounce cycles, ranging from eight debounce

cycles to 128 debounce cycles. See Table 11. Bits D[6:4]

specify the autorepeat rate or frequency ranging from

4â32 debounce cycles.

Only one autorepeat code is entered into the FIFO,

regardless of the number of keys pressed. The autore-

peat code continues to be entered in the FIFO at the

frequency set by bits D[3:0] until another key event is

recorded. Following the key-release event, if any keys are

still pressed, the device restarts the autorepeat sequence.

Autosleep Register (0x06)

Autosleep puts the device in sleep mode to draw minimal

current. When enabled, the device enters sleep mode

if no keys are pressed for the autoshutdown time. See

Table 12.

Key-Switch Array Size Register (0x30)

Bits D[7:4] set the row size of the key-switch array, and

bits D[3:0] set the column size of the key-switch array.

See Table 13. Set the bits to 0 if no key switches are

used. The key-switch array should be connected begin-

ning at ROW0 and COL0. If not used as a key-switch

matrix pin, then the pin can function as a GPIO port.

Key-Switch Sleep Mode

In sleep mode, the device draws minimal current. Switch-

matrix current sources are turned off and pulled up to

VCC. When autosleep is enabled, key-switch inactivity

for a period longer than the autosleep time puts the part

into sleep mode (FIFO data is maintained). Writing a 1 to

D7 or a keypress can take the device out of sleep mode.

Bit D7 in the configuration register gives the sleep-mode

status and can be read any time.

Autowake

Keypresses initiate autowake and the device goes into

operating mode. Keypresses that autowake the device

are not lost. When a key is pressed while the device is in

sleep mode, all analog circuitry, including switch-matrix

current sources, turn on in 2ms. The initial key needs to

be pressed for 2ms plus the debounce time to be stored

in the FIFO. Write a 0 to bit D1 in the configuration regis-

ter (0x01) to disable autowake.

FIFO Overflow

The FIFO overflow status occurs when the FIFO is full

(16 bytes) and additional events occur. If key release is

disabled, then the FIFO overflow status occurs when the

FIFO is full and not upon additional key events. When

the FIFO is overflowed, the first byte read from the FIFO

buffer is the overflow byte (0x7F). The order of the

original 16 bytes of event data is preserved, but further

events could be lost. When the FIFO is full, if the 18th

key event is a key release, then the FIFO overflow status

is removed.

GPIOs

The device has 16 GPIO ports, four of which have LED

control functions. The ports can be used as logic inputs

or logic outputs. COL7âCOL4 are also configurable as

constant-current PWM LED drivers. Each portâs logic

level is referenced to VCC or VLA. The GPIO portsâ inputs

can also be debounced. When in PWM mode, the ports

are set up to start their PWM cycle in 45N phase incre-

ments. This prevents large current spikes on the LED

supply voltage when driving multiple LEDs.

LED Driver Enable Register (0x31)

Bits D[3:0] correspond to COL7âCOL4 on the device.

Set the corresponding bit to 1 for enabling the LED driver

circuitry and 0 for normal GPIO function. See Table 14.

GPIO Direction 1 and 2 Registers (0x34, 0x35)

These registers configure the pins as an input or an output

port. GPIO Direction 1 register bits D[7:0] correspond with

ROW7âROW0. See Table 15. GPIO Direction 2 register

bits D[7:0] correspond with COL7âCOL0. See Table 16.

Set the corresponding bit to 0 to configure as input and 1

to configure as output.

When the port is initially programmed as an input, there

is a delay of one debounce period prior to detecting

a transition on the input port. This is to prevent a false

interrupt from occurring when changing a port from an

output to an input.

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