MAX16904 Datasheet, PDF (11/14 Pages) Maxim Integrated Products – 2.1MHz, High-Voltage, 600mA Mini-Buck Converter Thermal Shutdown Protection

2.1MHz, High-Voltage,
600mA Mini-Buck Converter
ESR of the input capacitor). The total voltage ripple is
the sum of ΔV_Q and ΔV_ESR. Assume the input-voltage
ripple from the ESR and the capacitor discharge is
equal to 50% each. The following equations show the
ESR and capacitor requirement for a target voltage rip-
ple at the input:
ESR
=
ΔV_ESR
⎛
⎝⎜
I_OUT
+
ΔI_{P − P}
2
⎞
⎠⎟
C_IN
=
I_OUT ×
ΔV_Q
D(1− D)
× f_SW
where:
ΔI_{P − P}
=
(V_IN − V_OUT ) × V_OUT
V_IN × f_SW × L
and:
D = ^VOUT
V_IN
where I_OUT is the output current, D is the duty cycle,
and f_SW is the switching frequency. Use additional
input capacitance at lower input voltages to avoid pos-
sible undershoot below the UVLO threshold during tran-
sient loading.
Output Capacitor
The allowable output-voltage ripple and the maximum
deviation of the output voltage during step load cur-
rents determine the output capacitance and its ESR.
The output ripple comprises of ΔV_Q (caused by the
capacitor discharge) and ΔV_ESR (caused by the ESR of
the output capacitor). Use low-ESR ceramic or alu-
minum electrolytic capacitors at the output. For alu-
minum electrolytic capacitors, the entire output ripple is
contributed by ΔV_ESR. Use the ESR_OUT equation to cal-
culate the ESR requirement and choose the capacitor
accordingly. If using ceramic capacitors, assume the
contribution to the output ripple voltage from the ESR
and the capacitor discharge to be equal. The following
equations show the output capacitance and ESR
requirement for a specified output-voltage ripple.
ESR = ^ΔVESR
ΔI_{P − P}
C_OUT
=
ΔI_{P − P}
8 × ΔV_Q × f_SW
where:
ΔI_{P − P}
=
(V_IN − V_OUT ) × V_OUT
V_IN × f_SW × L
V_{OUT _ RIPPLE} ≅ ΔV_ESR + ΔV_Q
ΔI_P-P is the peak-to-peak inductor current as calculated
above and f_SW is the converter’s switching frequency.
The allowable deviation of the output voltage during
fast transient loads also determines the output capaci-
tance and its ESR. The output capacitor supplies the
step load current until the converter responds with a
greater duty cycle. The response time (t_RESPONSE)
depends on the closed-loop bandwidth of the convert-
er. The device’s high switching frequency allows for a
higher closed-loop bandwidth, thus reducing
t_RESPONSE and the output capacitance requirement.
The resistive drop across the output capacitor’s ESR
and the capacitor discharge causes a voltage droop
during a step load. Use a combination of low-ESR tan-
talum and ceramic capacitors for better transient load
and ripple/noise performance. Keep the maximum out-
put-voltage deviations below the tolerable limits of the
electronics being powered. When using a ceramic
capacitor, assume an 80% and 20% contribution from
the output capacitance discharge and the ESR drop,
respectively. Use the following equations to calculate
the required ESR and capacitance value:
ESR_OUT
=
ΔV_ESR
I_STEP
C_OUT
= ^ISTEP
× t_RESPONSE
ΔV_Q
where I_STEP is the load step and t_RESPONSE is the
response time of the converter. The converter response
time depends on the control-loop bandwidth.
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching
power losses and clean stable operation. Use a multilayer
board wherever possible for better noise immunity. Refer
to the MAX16904 Evaluation Kit for recommended PCB
layout. Follow these guidelines for a good PCB layout:
1) The input capacitor (4.7μF, see the applications
schematic in the Typical Operating Circuits) should be
placed right next to the SUP pins (pins 2 and 3 on the
TSSOP-EP package). Because the device operates at
2.1MHz switching frequency, this placement is critical
for effective decoupling of high-frequency noise from
the SUP pins.
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