MAX13481E Datasheet, PDF (11/19 Pages) Maxim Integrated Products – ±15kV ESD-Protected USB Transceivers with External/Internal Pullup Resistors

±15kV ESD-Protected USB Transceivers with
External/Internal Pullup Resistors
Timing Diagrams
V_OHD
t_FR, t_LR
90%
t_FF, t_LF
90%
10%
10%
V_OLD
Figure 1. Rise and Fall Times
OE
D+/D-
VP/VM CONNECTED TO GND,
D+/D- CONNECTED
TO PULLUP
t_{PLZ_DRV}
VP AND VM RISE/FALL TIMES < 4ns
VM
OE
VP
t_{PLH_DRV}
t_{PHL_DRV}
D-
V_{CRS_F} , V_{CRS_L}
D+
D+/D-
t_{PHZ_DRV}
t_{PZL_DRV}
VP/VM CONNECTED TO V_L,
D+/D- CONNECTED
TO PULLDOWN
t_{PZH_DRV}
Figure 2. Timing of VP and VM to D+ and D-
stand voltage measured to IEC 61000-4-2 generally is
lower than that measured using the Human Body
Model. Figure 8 shows the IEC 61000-4-2 model. The
Contact Discharge method connects the probe to the
device before the probe is charged.
Machine Model
The Machine Model for ESD tests all connections using
a 200pF storage capacitor and zero discharge resis-
Figure 3. Driver’s Enable and Disable Timing
tance. Its objective is to emulate the stress caused by
contact that occurs with handling and assembly during
manufacturing. All pins require this protection during
manufacturing, not just inputs and outputs. After PC
board assembly, the Machine Model is less relevant to
I/O ports.
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