MAX11100 Datasheet, PDF (11/19 Pages) Maxim Integrated Products – 16-Bit, +5V, 200ksps ADC with 10μA Shutdown

MAX11100
16-Bit, +5V, 200ksps ADC with 10µA Shutdown
CS
SCLK
DOUT
tDV
1
tCSS
4
6
8
12
16
20
24
tCL
tCH
tCSH
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
tACQ
tDO
tTR
Figure 6. External Timing Diagram
COMPLETE CONVERSION SEQUENCE
CS
DOUT
TIMING NOT TO SCALE.
CONVERSION 0
POWERED UP
POWERED DOWN
CONVERSION 1
POWERED UP
Figure 7. Shutdown Sequence
Variations in frequency, duty cycle, or other aspects of
the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence. The
analog input is stored in the capacitive DAC, DOUT
changes from high impedance to logic-low, and the ADC
begins to convert after the sixth clock cycle. SCLK drives
the conversion process and shifts out the conversion
result on DOUT.
SCLK begins shifting out the data (MSB first) after the fall-
ing edge of the 8th SCLK pulse. Twenty-four falling clock
edges are needed to shift out the eight leading zeros
and 16 data bits. Extra clock pulses occurring after the
conversion result has been clocked out, and prior to the
rising edge of CS, produce trailing zeros at DOUT and
have no effect on the converter operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX11100 in
shutdown. For maximum throughput, force CS low again
to initiate the next conversion immediately after the speci-
fied minimum time (t_CSW).
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX11100 in shutdown.
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