DS3065WP Datasheet, PDF (11/15 Pages) Maxim Integrated Products – 3.3V, 8Mb, Nonvolatile SRAM with Clock

3.3V, 8Mb, Nonvolatile SRAM with Clock
Clock Operations
RTC Read Mode
The device executes an RTC read cycle whenever CE
(SRAM chip enable) and WE (write enable) are inactive
(high) and CS (RTC chip select) is active (low). The least
significant four address inputs (A0–A3) define which of
the 16 RTC registers is to be accessed (see Table 3).
Valid data is available to the eight data-output drivers
within tACC (access time) after the last address input
signal is stable, provided that CS and OE (output enable)
access times are also satisfied. If CS and OE access
times are not satisfied, data access must be measured
from the later-occurring signal (CS or OE) and the limit-
ing parameter is either tCO for CS or tOEC for OE rather
than address access.
RTC Write Mode
The device executes an RTC write cycle whenever CE
is inactive (high) and the CS and WE signals are active
(low) after address inputs are stable. The later-occurring
falling edge of CS or WE determines the start of the write
cycle. The write cycle is terminated by the earlier rising
edge of CS or WE. All address inputs must be kept valid
throughout the write cycle. WE must return to the high
state for a minimum recovery time (tWR) before another
cycle can be initiated. The CE and OE control signals
should be kept inactive (high) during RTC write cycles
to avoid bus contention. However, if the output drivers
have been enabled (CS and OE active), WE disables the
outputs in tODW from its falling edge.
Clock Oscillator Mode
The oscillator can be turned off to minimize current
drain from the battery. The OSC bit is the MSB of the
SECONDS register (B7 of F9h). Setting OSC to 1 stops
the oscillator; setting OSC to 0 starts the oscillator. The
initial state of OSC is not guaranteed. When power is
applied for the first time, the OSC bit should be enabled.
Reading the Clock
When reading the RTC data, it is recommended to halt
updates to the external set of double-buffered RTC reg-
isters. This puts the external registers into a static state,
allowing the data to be read without register values
changing during the read process. Normal updates to
the internal registers continue while in this state.
External updates are halted by writing a 1 to the read
bit (R). As long as a 1 remains in the R bit, updating is
inhibited. After a halt is issued, the registers reflect the
RTC count (day, date, and time) that was current at the
moment the halt command was issued. Normal updates
to the external set of registers resume within one second
after the R bit is set to 0 for a minimum of 500Fs. The R bit
must be 0 for a minimum of 500Fs to ensure the external
registers have fully updated.
Setting the Clock
As with a clock read, it is also recommended to halt
updates prior to setting new time values. Setting the write
bit (W) to 1 halts updates of the external RTC registers
8h–Fh. After setting the W bit to 1, the RTC registers can
be loaded with the desired count (day, date, and time)
in BCD format. Setting the W bit to 0 then transfers the
values written to the internal registers and allows normal
clock operation to resume.
Using the Clock Alarm
The alarm settings and control for the device reside
within RTC registers 2h–5h. The INTERRUPTS register
(6h) contains two alarm-enable bits: alarm flag enable
(AE) and alarm in backup-mode enable (ABE).
The alarm can be programmed to activate on a specific
day of the month or repeat every day, hour, minute, or
second. Alarm mask bits AM[4:1] control the alarm mode
(Table 2). Configurations not listed in the table default to
the once-per-second mode to notify the user of an incor-
rect alarm setting.
Table 2. Alarm Mask Bits
AM4
1
1
1
1
0
AM3
1
1
1
0
0
AM2
1
1
0
0
0
AM1
1
0
0
0
0
ALARM RATE
Once per second
When seconds match
When minutes and seconds match
When hours, minutes, and seconds match
When date, hours, minutes, and seconds match
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