MAX4747 Datasheet, PDF (10/15 Pages) Maxim Integrated Products – 50 Low-Voltage, Quad SPST/Dual SPDT Analog Switches in UCSP

50Ω Low-Voltage, Quad SPST/Dual SPDT Analog
Switches in UCSP
Test Circuits/Timing Diagrams (continued)
MAX4747–
MAX4750
V_{N_}
NO_
OR NC_
V+
V+
COM_
LOGIC
INPUT
IN_
GND
R_L
300Ω
V_OUT
C_L
35pF
C_L INCLUDES FIXTURE AND STRAY CAPACITANCE.
R_L
V_OUT = V_{N_} ( _{RL + RON} )
Figure 2. Switching Time
LOGIC ^VIH
INPUT
V_IL
SWITCH
OUTPUT
0
t_r < 5ns
t_f < 5ns
50%
t_OFF
V_OUT
0.9 x V_OUT
0.9 x V_OUT
t_ON
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
MAX4749
V+
V_{N_}
NO_
NC_
V+
COM_
COM_
IN_
LOGIC
INPUT
IN_
GND
V_OUT2
R_L2
300Ω
C_L2
35pF
V_OUT1
R_L1
C_L1
300Ω
35pF
C_L INCLUDES FIXTURE AND STRAY CAPACITANCE.
Figure 3. Break-Before-Make Interval
LOGIC ^VIH
INPUT
V_IL
SWITCH
OUTPUT 1
(V_OUT1) ₀
SWITCH
OUTPUT 2
(V_OUT2)
0
t_r < 5ns
t_f < 5ns
50%
0.9 x V_0UT1
0.9 x V_OUT2
t_BBM
t_BBM
MAX4747–
MAX4750
V_GEN
R_GEN
NC_
OR NO_
GND
V+
V+
COM
IN_
V_ILTO V_IH
Figure 4. Charge Injection
V_OUT
C_L
1nF
V_OUT
IN
OFF
∆V_OUT
OFF
ON
ON
OFF
OFF
IN
Q = (∆V_OUT)(C_L)
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
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