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MAX458 Datasheet, PDF (10/16 Pages) Maxim Integrated Products – 8x4 Video Crosspoint Switches with Buffers
8x4 Video Crosspoint Switches with Buffers
to their switch registers. As long as either –W—R– or –C—E– is
high, the input register will not change. The switch reg-
i–U—sPt—eD—r A—wT—ilE–l .pass any new data on the falling transition of
Each register
inputs to one
aomf pthliefiesrw. itWchit-hre–Ug—iP—sDt—eA—r T—bE–anlokwc, othnetroslws ittchhe
registers are transparent and
trolled by the input register.
swHiotcwhecveorn,nief c–Ut—ioP—nD—Ai—sT—cE–onis-
high, the switch register is latched and any change in
data by the input register will not affect the amplifier
output state. Two register banks are used so that data
can be loaded into input registers without affecting the
switch/amplifier selection. This allows amplifiers to be
programmed and then changed simultaneously. When
the registers are not latched, they are made transparent.
Use data bit D3 to disable the amplifier selected by
A0–A1 and place its output in high-impedance mode.
As an example, the code to disable OUT0 is as follows:
Pin Name: D3 D2 D1 D0 A1 A0
Input Code: 1 X X X 0 0
When operating in parallel mode, C—S– must be wired high
and SCLK and DIN should be grounded, as shown in
Figure 3. Refer to Figure 4 for the correct timing rela-
tionships.
Digital Section—Serial Mode
The MAX458/MAX459 use a three-wire serial interface
that is compatible with SPI, QPSI and Microwire inter-
fwahceens.–W—R–S,e–Ur—iPa—Dl—Am—T—oE–d,ea,nsdh–Co—Ew– nareinhFeilgduhriegh5a, nisd eC–—nS–agboleeds
low. Figures 6 and 7 show serial-mode timing. Figure 8
shows the MAX458/MAX459 configured for serial oper-
ation. Figure 9 shows the Microwire connection, and
Figure 10 shows the SPI/QSPI connection.
The serial output, DOUT, allows cascading of two or
more crosspoint switches to create larger arrays. The
data at DOUT is delayed by 16 cycles plus one clock
pulse
edge
width
when
C–—aS–t
DisINlo.w.DWOUheTnc–Ch—Sa–nisgehsigohn,
SCLK’s falling
DOUT remains
in the state of the last data bit.
The MAX458/MAX459 input data in 16-bit blocks. SPI
and Microwire interfaces output data in 8-bit blocks,
thereby requiring two write cycles to input data. The
QSPI interface allows variable word lengths from 8 to 16
bits and can be loaded into the crosspoint in one write
cycle. SPI and Microwire limit clock rates to 2MHz, while
the QSPI maximum clock rate is 4MHz.
A0/A1
ADDRESS VALID
tADS
tADH
CE
tCES
tCEH
tWR
WR
tDS
tDH
tUPS
D0–D3
DATA VALID
tWRS
UPDATE
tUP
Figure 4. Parallel-Mode Timing
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