MAX3672 Datasheet, PDF (10/12 Pages) Maxim Integrated Products – Low-Jitter 155MHz/622MHz Clock Generator

Low-Jitter 155MHz/622MHz Clock Generator
Interface Schematics
V_CC
V_CC - 1.3V
10.5kΩ
REFLCK+
REFLCK-
10.5kΩ
MAX3672
V_CC
OUT+
OUT-
MAX3672
Figure 1. Input Interface
LOL
60kΩ
0.6V
REFCLK
VCO
60kΩ
MAX3672
THADJ
CTH
Figure 3. Loss-of-Lock Indicator
Figure 2. Output Interface
a VCO, the user needs to take into account the VCO’s
phase noise and modulation bandwidth. Phase noise is
important because the phase noise above the PLL band-
width is dominated by the VCO noise performance.
The modulation bandwidth of the VCO contributes an
additional higher-order pole (HOP) to the system and
should be greater than the HOP set with the external filter
components.
Noise Performance Optimization
Depending on the application, there are many different
ways to optimize the PLL performance. The following
are general guidelines to improve the noise on the sys-
tem output clock.
1) If the reference clock noise dominates the total sys-
tem-clock output jitter, then decreasing the loop
bandwidth (K) reduces the output jitter.
2) If the VCO noise dominates the total system clock
output jitter, then increasing the loop bandwidth (K)
reduces the output jitter.
3) Smaller total divider ratio (N1 ✕ N2), lower HOP, and
smaller R₁ reduce the spurious output jitter.
4) Smaller R₁ reduces the random noise due to the op amp.
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