MAX1951A Datasheet, PDF (10/12 Pages) Maxim Integrated Products – 1MHz, 2A, 2.6V to 5.5V Input, PWM DC-DC Step-Down Regulator with Enable

1MHz, 2A, 2.6V to 5.5V Input, PWM DC-DC
Step-Down Regulator with Enable
R_LOAD = V_OUT/I_OUT(MAX) = 1.5V/2A = 0.75Ω
fp_MOD = [1/(2π x C_OUT x (R_LOAD + R_ESR)]
= [1/(2 x π x10 x10^-6 x (0.75 + 0.01)] = 20.9Hz.
fz_ESR = [1/(2π x C_OUT x R_ESR)]
= [1/(2 x π x 10 x10^-6 x 0.01)] = 1.59MHz.
For a 2µH output inductor, pick the closed-loop unity-
gain crossover frequency (f_C) at 200kHz. Determine the
power modulator gain at f_C:
G_MOD(fc) = gmc x R_LOAD x fp_MOD/f_C = 4.2 x 0.75 x
20.9kHz/200kHz = 0.33
then:
R₁ = V_O x K/(g_mEA x V_FB x G_MOD(fC)) = (1.5 x
0.55)/(60 x 10^-6 x 0.8 x 0.33) ≈ 52.3kΩ (1%)
C₂ = (2 x V_OUT x C_OUT)/R₁ x I_OUT(MAX)
= (2 x 1.5 x 10 x 10^-6)/(52.3kΩ x 2)
≈ 143pF, choose 150pF, 10%
Applications Information
PCB Layout Considerations
Careful PCB layout is critical to achieve clean and sta-
ble operation. The switching power stage requires par-
ticular attention. Follow these guidelines for good PCB
layout:
1) Place decoupling capacitors as close as possible to
the IC. Keep the power ground plane (connected to
PGND) and signal ground plane (connected to
GND) separate.
2) Connect input and output capacitors to the power
ground plane; connect all other capacitors to the
signal ground plane.
3) Keep the high-current paths as short and wide as
possible. Keep the path of switching current (C1 to IN
and C1 to PGND) short. Avoid vias in the switching
paths.
4) If possible, connect IN, LX, and PGND separately to
a large copper area to help cool the IC to further
improve efficiency and long-term reliability.
5) Ensure all feedback connections are short and
direct. Place the feedback resistors as close as pos-
sible to the IC.
6) Route high-speed switching nodes away from sensi-
tive analog areas (FB, COMP).
Thermal Considerations
See the MAX1951A Evaluation Kit for an optimized lay-
out example. Thermal performance can be further
improved with one of the following options:
1) Increase the copper areas connected to GND, LX,
and IN.
2) Provide thermal vias next to GND and IN, to the
ground plane and power plane on the back side of
PCB with openings in the solder mask next to the
vias to provide better thermal conduction.
3) Provide forced-air cooling to further reduce case
temperature.
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