MAX1552 Datasheet, PDF(10/12 Page) Maxim Integrated Products

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MAX1552 Datasheet, PDF (10/12 Pages) Maxim Integrated Products – Complete Power IC for Low-Cost PDAs

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Complete Power IC for

Low-Cost PDAs

VIN

FEEDBACK

RESISTORS

SIMPLIFIED DC-TO-DC CONVERTER

AVDD

VDOUT

DAC

ERROR AMP

VREF

1.25V

CONTROL

VOUT

(LCD BIAS)

MAX1552

Figure 3. Adjusting the Output Voltage with a DAC

The circuit consists of the PWM source, capacitor C10,

and resistors RD and RW. To analyze the transfer func-

tion of the PWM circuit, it is easiest to first simplify it to

its Thevenin equivalent. The Thevenin voltage can be

calculated using the following formula:

VTHEV = (D x VOH) + (1 - D) x VOL

where D is the duty cycle of the PWM signal, VOH is the

PWM output high level (often 3.3V), and VOL is the

PWM output low level (usually 0V). For CMOS logic this

equation simplifies to:

VTHEV = D x VDD

where VDD is the I/O voltage of the PWM output. The

Thevenin impedance is the sum of resistors RW and RD:

RTHEV = RD + RW

The output voltage (VOUT) as a function of the PWM

average voltage (VTHEV) is:

( ) VOUT

1.25

ï£«

ï£ï£¬1+

ï£«

ï£ï£¬

R1ï£¶

R2 ï£¸ï£·

ï£¶

ï£¸ï£·

1.25

â VTHEV

R THEV

Ã R1

When using the PWM adjustment method, RD isolates

the capacitor from the feedback loop of the MAX1552.

The cutoff frequency of the lowpass filter is defined as:

2Ã

Ï Ã RTHEV Ã C10

The cutoff frequency should be at least two decades

below the PWM frequency to minimize the induced AC

ripple at the output.

An important consideration is the turn-on transient cre-

ated by the initial charge on filter capacitor C10. This

capacitor forms a time constant with RTHEV, which

causes the output to initialize at a higher-than-intended

voltage. This overshoot can be minimized by scaling

RD as high as possible compared to R1 and R2.

Alternatively, the ÂµP can briefly keep the LCD disabled

until the PWM voltage has had time to stabilize.

PC Board Layout and Grounding

Careful PC board layout is important for minimizing

ground bounce and noise. Keep the MAX1552âs ground

pin and the ground leads of the input and output capaci-

tors less than 0.2in (5mm) apart. In addition, keep all

connections to FB and LX as short as possible. In partic-

ular, external feedback resistors should be as close to

FB as possible. To minimize output voltage ripple, and to

maximize output power and efficiency, use a ground

plane and solder GND directly to the ground plane.

Refer to the MAX1552 evaluation kit for a layout example.

Thermal Considerations

In most applications, the circuit is located on a multilay-

er board and full use of the four or more layers is rec-

ommended. For heat dissipation, connect the exposed

backside pad of the QFN package to a large analog

ground plane, preferably on a surface of the board that

receives good airflow. Typical applications use multiple

ground planes to minimize thermal resistance. Avoid

large AC currents through the analog ground plane.

10 ______________________________________________________________________________________

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