MAX14780E_11 Datasheet, PDF (10/14 Pages) Maxim Integrated Products – 5.0V, 30kV ESD-Protected, Fail-Safe, Hot-Swap, RS-485/RS-422 Transceiver

+5.0V, ±30kV ESD-Protected, Fail-Safe,
Hot-Swap, RS-485/RS-422 Transceiver
Detailed Description
The MAX14780E high-speed transceiver for RS-485/
RS-422 communication contains one driver and one
receiver. This device features fail-safe circuitry, which
guarantees a logic-high receiver output when the receiv-
er inputs are open or shorted, or when they are con-
nected to a terminated transmission line with all drivers
disabled (see the Fail-Safe section). The MAX14780E
also features a hot-swap capability allowing line inser-
tion without erroneous data transfer (see the Hot-Swap
Capability section). The MAX14780E features reduced
slew-rate drivers that minimize EMI and reduce reflec-
tions caused by improperly terminated cables, allowing
error-free data transmission up to 500kbps.
The MAX14780E is a half-duplex transceiver and oper-
ates from a single +5.0V supply. Drivers are output
short-circuit current limited. Thermal-shutdown circuitry
protects drivers against excessive power dissipation.
When activated, the thermal-shutdown circuitry places
the driver outputs into a high-impedance state.
Fail-Safe
The MAX14780E guarantees a logic-high receiver output
when the receiver inputs are shorted or open, or when
they are connected to a terminated transmission line with
all drivers disabled. This is done by setting the receiver
input threshold between -50mV and -200mV. If the dif-
ferential receiver input voltage (A - B) is greater than or
equal to -50mV, RO is logic-high. If (A - B) is less than
or equal to -200mV, RO is logic-low. In the case of a ter-
minated bus with all transmitters disabled, the receiver’s
differential input voltage is pulled to 0V by the termina-
tion. With the receiver threshold of the MAX14780E,
this results in a logic-high with a 50mV minimum noise
margin. Unlike previous fail-safe devices, the -50mV to
-200mV threshold complies with the ±200mV EIA/TIA-
485 standard.
Hot-Swap Capability
Hot-Swap Inputs
When circuit boards are inserted into a hot or powered
backplane, differential disturbances to the data bus
can lead to data errors. Upon initial circuit board inser-
tion, the data communication processor undergoes
its own power-up sequence. During this period, the
processor’s logic-output drivers are high impedance
and are unable to drive the DE and RE inputs of these
devices to a defined logic level. Leakage currents up
to ±10μA from the high-impedance state of the proces-
sor’s logic drivers could cause standard CMOS enable
inputs of a transceiver to drift to an incorrect logic level.
Additionally, parasitic circuit board capacitance could
cause coupling of VCC or GND to the enable inputs.
Without the hot-swap capability, these factors could
improperly enable the transceiver’s driver or receiver.
When VCC rises, an internal pulldown circuit holds DE
low and RE high. After the initial power-up sequence,
the pulldown circuit becomes transparent, resetting the
hot-swap tolerable input.
Hot-Swap Input Circuitry
The enable inputs feature hot-swap capability. At the
input there are two nMOS devices, M1 and M2 (Figure 9).
When VCC ramps from zero, an internal 7μs timer turns
on M2 and sets the SR latch, which also turns on M1.
Transistors M2, a 1.5mA current sink, and M1, a 500μA
current sink, pull DE to GND through a 5kΩ resistor.
M2 is designed to pull DE to the disabled state against
an external parasitic capacitance up to 100pF that can
drive DE high. After 7μs, the timer deactivates M2 while
M1 remains on, holding DE low against three-state leak-
ages that can drive DE high. M1 remains on until an
external source overcomes the required input current.
At this time, the SR latch resets and M1 turns off. When
M1 turns off, DE reverts to a standard, high-impedance
VCC
TIMER
TIMER
10µs
SR LATCH
5kΩ
DE
100µA
500µA
M1
M2
DE
(HOT SWAP)
Figure 9. Simplified Structure of the Driver Enable Pin (DE)
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