MAX146 Datasheet, PDF (10/24 Pages) Maxim Integrated Products – +2.7Low-Power, 8-Channel, Serial 12-Bit ADCs

+2.7V, Low-Power, 8-Channel,
Serial 12-Bit ADCs
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
t_ACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by the following
equation:
t_ACQ = 9 x (R_S + R_IN) x 16pF
where R_IN = 9kΩ, R_S = the source impedance of the
input signal, and t_ACQ is never less than 1.5µs. Note
that source impedances below 1kΩ do not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to V_DD and AGND, allow the channel input pins to swing
from AGND - 0.3V to V_DD + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed V_DD by more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of
off channels over 2mA.
Quick Look
To quickly evaluate the MAX146/MAX147’s analog per-
formance, use the circuit of Figure 5. The MAX146/
MAX147 require a control byte to be written to DIN
before each conversion. Tying DIN to +3V feeds in con-
trol bytes of $FF (HEX), which trigger single-ended
unipolar conversions on CH7 in external clock mode
without powering down between conversions. In exter-
nal clock mode, the SSTRB output pulses high for one
clock period before the most significant bit of the 12-bit
conversion result is shifted out of DOUT. Varying the
analog input to CH7 will alter the sequence of bits from
DOUT. A total of 15 clock cycles is required per con-
version. All transitions of the SSTRB and DOUT outputs
occur on the falling edge of SCLK.
OSCILLOSCOPE
0V TO
2.500V
ANALOG
INPUT 0.01µF
+3V
V_OUT
MAX872
COMP
1000pF
MAX146
MAX147
CH7
+3V
REFADJ
2.5V
VREF
C1
0.1µF
V_DD
DGND
AGND
COM
CS
SCLK
DIN
DOUT
SSTRB
SHDN
+3V
N.C.
OPTIONAL FOR MAX146,
REQUIRED FOR MAX147
+3V
0.1µF
SCLK
2MHz
OSCILLATOR
SSTRB
DOUT*
CH1
CH2
CH3
CH4
* FULL-SCALE ANALOG INPUT, CONVERSION RESULT = $FFF (HEX)
Figure 5. Quick-Look Circuit
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