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MAX12527 Datasheet, PDF (10/28 Pages) Maxim Integrated Products – Dual, 65Msps, 12-Bit, IF/Baseband ADC
Dual, 65Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL ≈ 5pF at digital outputs, VIN = -0.5dBFS,
DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 65MHz (50% duty cycle), TA = +25°C, unless otherwise noted.)
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
(fCLK = 65.00352MHz, fIN = 175MHz)
90
85
SFDR
80
75
-THD
70
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 65.00352MHz, fIN = 70MHz)
72
SNR
70
68
SINAD
66
64
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 65.00352MHz, fIN = 70MHz)
90
85
SFDR
80
-THD
75
70
65
62
65
60
3.0 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 65.00352MHz, fIN = 175MHz)
72
SNR
70
68
SINAD
66
64
60
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
OVDD (V)
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 65.00352MHz, fIN = 175MHz)
90
85
SFDR
80
75
-THD
70
62
65
60
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
OVDD (V)
60
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
OVDD (V)
PDISS, IOVDD (DIGITAL) vs. DIGITAL SUPPLY VOLTAGE
SNR, SINAD vs. CLOCK DUTY CYCLE
(fCLK = 65.00352MHz, fIN = 175MHz)
(fIN = 70MHz, AIN = -0.5dBFS)
80
72
CL ≈ 5pF
70
SNR
70
60
50
PDISS (DIGITAL)
40
68
SINAD
66
30
IOVDD
20
10
0
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
OVDD (V)
64
62
60
25
SINGLE-ENDED CLOCK INPUT DRIVE
35
45
55
65
75
CLOCK DUTY CYCLE (%)
60
1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6
OVDD (V)
PDISS, IVDD (ANALOG) vs. ANALOG SUPPLY VOLTAGE
(fCLK = 65.00352MHz, fIN = 175MHz)
900
800
PDISS (ANALOG)
700
600
500
400
IVDD
300
200
100
0
3.0 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
-THD, SFDR vs. CLOCK DUTY CYCLE
(fIN = 70MHz, AIN = -0.5dBFS)
90
SFDR
85
80
-THD
75
70
65
60
25
SINGLE-ENDED CLOCK INPUT DRIVE
35
45
55
65
75
CLOCK DUTY CYCLE (%)
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