MAX1200 Datasheet, PDF (10/16 Pages) Maxim Integrated Products – +5v sINGLE-sUPPLY, 1mSPS, 16-bIT sELF-cALIBRATING adc

+5V Single-Supply, 1Msps, 16-Bit
Self-Calibrating ADC
Analog Signal Conditioning
For single-ended inputs, the negative analog input pin
(INN) is connected to the common-mode voltage pin
(CM) and the positive analog input pin (INP) is connect-
ed to the input.
To take full advantage of the ADC’s superior AC perform-
ance up to the Nyquist frequency, drive the chip with
differential signals. In communication systems the sig-
nals may inherently be available in differential mode;
however medical and/or other applications may only
provide single-ended inputs. In this case, convert the
single-ended signals into differential ones by using the
circuit recommended in Figure 5. Use low-noise, wide-
band amplifiers, such as the MAX4108, to maintain the
signal purity over the full-power bandwidth of the
MAX1200 input.
Lowpass or bandpass signals may be required to
improve the signal-to-noise and distortion of the incom-
ing signal. For low-frequency signals (<100kHz), active
filters may be used. For higher frequencies, passive fil-
ters are more convenient.
V+
IN
INP
MAX4108
CM
V-
V+
INN
MAX4108
V-
CM
Single-Ended to Differential
Conversion Using Transformers
An alternative single-ended to differential-ended con-
version method is a balun transformer such as the
CTX03-13675 from Coiltronics. An important benefit of
these transformers is their ability to level-shift single-
ended signals referred to ground on the primary side to
optimum common-mode voltages on the secondary
side. At frequencies below 20kHz the transformer core
begins to saturate, causing odd-order harmonics.
Clock Source Requirements
Pipelined ADCs typically need a 50% duty cycle clock.
To avoid this constraint, the MAX1200 provides a
divide-by-two circuit to relax this requirement. The
clock generator should be chosen commensurate with
the frequency range, amplitude, and slew rate of the
signal source. If the slew rate of the input signal is
small, the jitter requirement on the clock is relaxed.
However, if the slew rate is high, the clock jitter needs
to be kept at a minimum. For a full-scale amplitude
input sine wave, the maximum possible signal-to-noise
ratio (SNR) due completely to clock jitter is given by:
SNR_MAX
=
1
2⋅ π ⋅ f_IN ⋅ σ_JITTER
For example, if f_IN is 500kHz and σ_JITTER is 10ps RMS,
then the SNR limit due to jitter is about 90dB. Generating
such a clock source requires a low-noise comparator and
a low-phase-noise signal generator. The clock circuit
shown in Figure 6 is a possible solution.
V+
0.1µF
CLK_IN
1k
V+
5k _MAX961
0.1µF
CLK
0.1µF
1k
Figure 5. A simple circuit generates differential signals from a
single-ended input referred to analog ground. The common-
mode voltage at INP and INN is the same as CM.
Figure 6. Clock Generation Circuit Using Low-Noise Comparator
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