MAX9476 Datasheet, PDF (1/8 Pages) Maxim Integrated Products – Low-Jitter, 8kHz Reference Clock Synthesizer Outputs 35.328MHz

19-3530; Rev 0; 1/05
EVAALVUAAILTAIOBNLEKIT
Low-Jitter, 8kHz Reference
Clock Synthesizer Outputs 35.328MHz
General Description
The MAX9476 low-cost, high-performance clock syn-
thesizer with an 8kHz input reference clock provides six
buffered LVTTL clock outputs at 35.328MHz. The clock
synthesizer can be used to generate the clocks for sys-
tems using T1, E1, T3, E3, and xDSL.
The MAX9476 features a phase-lock loop (PLL) that uses
a voltage-controlled crystal oscillator (VCXO). The inter-
nal PLL phase locks the external crystal (35.328MHz) to
the 8kHz input reference clock. In addition, this device
generates a jitter-suppressed output that provides a bet-
ter source for the reference clock relay.
The MAX9476 is available in a 24-pin TSSOP package
and operates over the extended operating temperature
range of -40°C to +85°C and a single +3V to +3.6V
power-supply range. For using lower value external
crystals, refer to the MAX9486 data sheet.
Features
o 8kHz Input-Reference CLK
o 4ps_RMS (typ) Output Jitter
o High-Jitter Rejection on the Reference CLK
o Synthesizer Locks to the 8kHz Reference with a
±100ppm Range
o Output Frequency: 35.328MHz
o Six Buffered LVTTL Low-Jitter Outputs
o One 8kHz Reference CLK Relay Output
o +3.3V Supply Operation
o 24-Pin TSSOP Package
Applications
Telecom Equipment Using T1, E1, T3, E3, and
ISDN Protocols
xDSL Equipment in CO with Interface to the
Telecom Protocols
PART
MAX9476EUG
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-
PACKAGE
24 TSSOP
PKG
CODE
U24-1
Pin Configuration
TOP VIEW
SHDN 1
REO 2
REIN 3
V_DDP 4
GNDP 5
X1 6
V_DD 7
X2 8
GND 9
LP2 10
LP1 11
SETI 12
MAX9476
TSSOP
24 CLK1
23 GND
22 CLK2
21 V_DD
20 CLK3
19 V_DD
18 GND
17 CLK4
16 V_DD
15 CLK5
14 GND
13 CLK6
Typical Application Circuit
R₁
C₁
C₂
LP1 LP2 X1
X2
V_DDP
V_DD
SETI
CLK1
CLK2
R_SET
MAX9476
CLK3
GNDP
CLK4
V_DD
CLK5
SHDN
CLK6
REIN
REO
GND
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