MAX9396 Datasheet, PDF (1/13 Pages) Maxim Integrated Products – 2:1 Multiplexer and 1:2 Demultiplexer with Loopback

19-0736; Rev 0; 1/07
2:1 Multiplexer and 1:2 Demultiplexer
with Loopback
General Description
The MAX9396 consists of a 2:1 multiplexer and a 1:2
demultiplexer with loopback. The multiplexer section
(channel B) accepts two differential inputs and gener-
ates a single differential output. The demultiplexer sec-
tion (channel A) accepts a single differential input and
generates two parallel differential outputs. The
MAX9396 features a loopback mode that connects the
input of channel A to the output of channel B and con-
nects the selected input of channel B to the outputs of
channel A.
The differential inputs of the MAX9396 accept
CML/LVPECL levels and can also accept LVDS inputs
with common-mode voltages from +0.6V to (V_CC -
0.05V). The differential outputs are LVDS compatible
and drive 100Ω loads.
Three LVCMOS/LVTTL logic inputs control the internal
connections between inputs and outputs, one for the
multiplexer portion of channel B (BSEL), and the other
two for loopback control of channels A and B (LB_SELA
and LB_SELB). Independent enable inputs for each dif-
ferential output pair provide additional flexibility.
Fail-safe circuitry forces the outputs to a differential low
condition for undriven inputs or when the common-
mode voltage is below +0.6V.
Ultra-low 57ps_P-P (typ) pseudorandom bit sequence
(PRBS) jitter ensures reliable communications in high-
speed links that are highly sensitive to timing error,
especially those incorporating clock-and-data recovery,
or serializers and deserializers. The high-speed switch-
ing performance guarantees 1.25Gbps operation and
less than 87ps (max) skew between channels.
The MAX9396 is available in a 32-pin TQFP package
and is specified over the -40°C to +85°C extended tem-
perature range.
Applications
High-Speed Telecom/Datacom Equipment
Central Office Backplane Clock Distribution
DSLAMs
Protection Switching
Fault-Tolerant Systems
Pin Configuration and Functional Diagram appear at end of
data sheet.
Features
♦ Guaranteed 1.25Gbps Operation with 450mV (min)
Differential Output Swing
♦ Integrated 100Ω Resistors on Differential Inputs
♦ Simultaneous Loopback Control
♦ 2ps_(RMS) (max) Random Jitter
♦ AC Specifications Guaranteed for 150mV
Differential Input
♦ Signal Inputs Accept Any Differential Signals with
V_CM = +0.6V to (V_CC - 0.05V)
♦ LVDS Outputs for Clock or High-Speed Data
♦ Low-Level Input Fail-Safe Detection
♦ +3.0V to +3.6V Supply Voltage Range
♦ LVCMOS/LVTTL Logic Inputs
Ordering Information
PART
TEMP RANGE
MAX9396EHJ+ -40°C to +85°C
+Denotes a lead-free package.
PIN-
PACKAGE
32 TQFP
PKG
CODE
H32-1
Typical Operating Circuit
+3.0V TO
+3.6V
0.1µF
Z0 = 50Ω
0.01µF
VCC
INA
OUTA0
Z0 = 50Ω
LVCMOS/LVTTL
LOGIC INPUTS
INA
OUTA0
MAX9396
INB0
OUTA1
INB0
INB1
OUTA1
INB1
ENA0
OUTB
ENA1
ENB
OUTB
LB_SELA
LB_SELB
BSEL
GND GND GND GND
Z0 = 50Ω
100Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
LVDS
RECEIVER
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