MAX9394-MAX9395 Datasheet, PDF (1/13 Pages) Maxim Integrated Products – 2:1 Multiplexers and 1:2 Demultiplexers with Loopback

19-2878; Rev 0; 7/03
2:1 Multiplexers and 1:2 Demultiplexers with
Loopback
General Description
The MAX9394/MAX9395 consist of a 2:1 multiplexer
and a 1:2 demultiplexer with loopback. The multiplexer
section (channel B) accepts two low-voltage differential
signaling (LVDS) inputs and generates a single LVDS
output. The demultiplexer section (channel A) accepts
a single LVDS input and generates two parallel LVDS
outputs. The MAX9394/MAX9395 feature a loopback
mode that connects the input of channel A to the output
of channel B and connects the selected input of chan-
nel B to the outputs of channel A.
Three LVCMOS/LVTTL logic inputs control the internal
connections between inputs and outputs, one for the
multiplexer portion of channel B (BSEL), and the other
two for loopback control of channels A and B (LB_SELA
and LB_SELB). Independent enable inputs for each dif-
ferential output pair provide additional flexibility.
Fail-safe circuitry forces the outputs to a differential low
condition for undriven inputs or when the common-
mode voltage exceeds the specified range. The
MAX9394 provides high-level input fail-safe detection
for HSTL, LVDS, and other GND-referenced differential
inputs. The MAX9395 provides low-level fail-safe detec-
tion for CML, LVPECL, and other V_CC-referenced differ-
ential inputs.
Ultra low 91ps_P-P (max) pseudorandom bit sequence
(PRBS) jitter ensures reliable communications in high-
speed links that are highly sensitive to timing error,
especially those incorporating clock-and-data recovery,
or serializers and deserializers. The high-speed switch-
ing performance guarantees 1.5GHz operation and less
than 87ps (max) skew between channels.
LVDS inputs and outputs are compatible with the
TIA/EIA-644 LVDS standard. The LVDS outputs drive
100Ω loads. The MAX9394/MAX9395 are offered in 32-
pin TQFP and 28-pin thin QFN packages and operate
over the extended temperature range (-40°C to +85°C).
Applications
High-Speed Telecom/Datacom Equipment
Central Office Backplane Clock Distribution
DSLAM
Protection Switching
Fault-Tolerant Systems
Pin Configurations and Functional Diagram appear at end
of data sheet.
Features
o Guaranteed 1.5GHz Operation with 250mV
Differential Output Swing
o Simultaneous Loopback Control
o 2ps_(RMS) (max) Random Jitter
o AC Specifications Guaranteed for 150mV
Differential Input
o Signal Inputs Accept Any Differential Signaling
Standard
o LVDS Outputs for Clock or High-Speed Data
o High-Level Input Fail-Safe Detection (MAX9394)
o Low-Level Input Fail-Safe Detection (MAX9395)
o +3.0V to +3.6V Supply Voltage Range
o LVCMOS/LVTTL Logic Inputs
Ordering Information
PART
MAX9394EHJ
MAX9394ETI*
MAX9395EHJ
MAX9395ETI*
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
32 TQFP
28 Thin QFN
32 TQFP
28 Thin QFN
*Future product—contact factory for availability.
Typical Operating Circuit
+3.0V TO
+3.6V
0.1µF
0.01µF
VCC
Z0 = 50Ω
INA
100Ω
Z0 = 50Ω
INA
MAX9394
MAX9395
OUTA0
OUTA0
LVCMOS/LVTTL
LOGIC INPUTS
INB0
OUTA1
INB0
INB1
OUTA1
INB1
ENA0
OUTB
ENA1
ENB
OUTB
LB_SELA
LB_SELB
BSEL
GND GND GND GND
Z0 = 50Ω
100Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
Z0 = 50Ω
LVDS
RECEIVER
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