MAX9324 Datasheet, PDF (1/12 Pages) Maxim Integrated Products – One-to-Five LVPECL/LVCMOS Output Clock and Data Driver

19-2576; Rev 0; 10/02
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
General Description
The MAX9324 low-skew, low-jitter, clock and data driver
distributes a differential LVPECL input to four differential
LVPECL outputs and one single-ended LVCMOS output.
All outputs default to logic low when the differential inputs
equal GND or are left open. The MAX9324 operates from
3.0V to 3.6V, making it ideal for 3.3V systems, and con-
sumes only 25mA (max) of supply current.
The MAX9324 features low 150ps (max) part-to-part
skew, low 15ps output-to-output skew, and low 1.7ps
RMS jitter, making the device ideal for clock and data
distribution across a backplane or board. CLK_EN and
SEOUT_Z control the status of the various outputs.
Asserting CLK_EN low configures the differential (Q_,
Q_) outputs to a differential low condition and SEOUT to
a single-ended logic-low state. CLK_EN operation is
synchronous with the CLK_ inputs. A logic high on
SEOUT_Z places SEOUT in a high-impedance state.
SEOUT_Z is asynchronous with the CLK (CLK) inputs.
The MAX9324 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm ✕ 4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range.
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Base Station
ATE
Features
o 15ps Differential Output-to-Output Skew
o 1.7ps_RMS Added Random Jitter
o 150ps (max) Part-to-Part Skew
o 450ps Propagation Delay
o Synchronous Output Enable/Disable
o Single-Ended Monitor Output
o Outputs Assert Low when CLK, CLK are Open or
at GND
o 3.0V to 3.6V Supply Voltage Range
o -40°C to +85°C Operating Temperature Range
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX9324EUP
-40°C to +85°C 20 TSSOP
MAX9324ETP*
-40°C to +85°C 20 Thin QFN-EP**
*Future product—Contact factory for availability.
**EP = Exposed paddle.
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
Pin Configurations
TOP VIEW
SEOUT 1
GND 2
N.C. 3
SEOUT_Z 4
CLK 5
20 19 18 17 16
MAX9324
**EXPOSED PADDLE
15 VCC
14 Q1
13 Q1
12 Q2
11 Q2
6 7 8 9 10
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
GND 1
CLK_EN 2
N.C. 3
SEOUT 4
GND 5
N.C. 6
SEOUT_Z 7
CLK 8
CLK 9
VCC 10
MAX9324
TSSOP
20 Q0
19 Q0
18 VCC
17 Q1
16 Q1
15 Q2
14 Q2
13 VCC
12 Q3
11 Q3
________________________________________________________________ Maxim Integrated Products 1
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