MAX9320B Datasheet, PDF (1/7 Pages) Maxim Integrated Products – 1:2 Differential PECL/ECL/LVPECL/LVECL Clock and Data Driver

19-2383; Rev 1; 11/03
1:2 Differential PECL/ECL/LVPECL/LVECL
Clock and Data Driver
General Description
The MAX9320B low-skew, 1-to-2 differential driver is
designed for clock and data distribution. The input is
reproduced at two differential outputs. The differential
input can be adapted to accept single-ended inputs by
applying an external reference voltage.
The MAX9320B features ultra-low propagation delay
(208ps), part-to-part skew (20ps), and output-to-output
skew (6ps) with 30mA maximum supply current, mak-
ing this device ideal for clock distribution. For interfac-
ing to differential PECL and LVPECL signals, this
device operates over a +3.0V to +5.5V supply range,
allowing high-performance clock or data distribution in
systems with a nominal 3.3V or 5V supply. For differen-
tial ECL and LVECL operation, this device operates
from a -3.0V to -5.5V supply.
The MAX9320B is offered in industry-standard 8-pin
TSSOP and SO packages.
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Protection Switching
Features
o Improved Second Source of the MC10EP11D
o +3.0V to +5.5V Differential PECL/LVPECL
Operation
o -3.0V to -5.5V ECL/LVECL Operation
o Low 22mA Supply Current
o 20ps Part-to-Part Skew
o 6ps Output-to-Output Skew
o 208ps Propagation Delay
o Minimum 300mV Output at 3GHz
o Outputs Low for Open Input
o ESD Protection >2kV (Human Body Model)
PART
MAX9320BESA
MAX9320BEUA
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
8 SO
8 TSSOP
Pin Configuration
D
D
Q_
Q
(Q_) - (Q_)
V_IHD
V_IHD - V_ILD
V_ILD
t_PLHD
t_PHLD
V_OH
V_OH - V_OL
V_OL
80%
80%
0V (DIFFERENTIAL)
0V (DIFFERENTIAL)
20%
20%
t_R
t_F
Q0 1
Q0 2
Q1 3
Q1 4
MAX9320B
50kΩ ^80kΩ
60kΩ
100kΩ
8 VCC
7D
6D
5 VEE
TSSOP/SO
Figure 1. Differential Transition Time and Propagation Delay
Timing Diagram
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