MAX9320 Datasheet, PDF (1/9 Pages) Maxim Integrated Products – 1:2 Differential LVPECL/LVECL/HSTL Clock and Data Drivers

19-2201; Rev 0; 8/01
1:2 Differential LVPECL/LVECL/HSTL
Clock and Data Drivers
General Description
The MAX9320/MAX9320A are low-skew, 1-to-2 differen-
tial drivers designed for clock and data distribution. The
input is reproduced at two differential outputs. The dif-
ferential input can be adapted to accept single-ended
inputs by applying an external reference voltage.
The MAX9320/MAX9320A feature ultra-low propagation
delay (208ps), part-to-part skew (20ps), and output-to-
output skew (6ps) with 30mA maximum supply current,
making these devices ideal for clock distribution. For
interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.25V to +3.8V supply
range, allowing high-performance clock or data distrib-
ution in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.25V to -3.8V supply.
The pinout is the only difference between the MAX9320
and MAX9320A. Multiple pinouts are provided to simplify
routing across a backplane to either side of a double-
sided board.
These devices are offered in space-saving 8-pin SOT23*
and industry-standard TSSOP* and SO packages.
Applications
Precision Clock Distribution
Low-Jitter Data Repeater
Protection Switching
Features
o Improved Second Source of the MC10LVEP11
(MAX9320)
o +2.25V to +3.8V Differential HSTL/LVPECL
Operation
o -2.25V to -3.8V LVECL Operation
o Low 22mA (typ) Supply Current
o 20ps (typ) Part-to-Part Skew
o 6ps (typ) Output-to-Output Skew
o 208ps (typ) Propagation Delay
o Minimum 300mV Output at 3GHz
o Outputs Low for Open Input
o ESD Protection >2kV (Human Body Model)
o Available in Thermally Enhanced Exposed-Pad
SO Package
Ordering Information
PART
TEMP.
RANGE
PIN-
PACKAGE
MAX9320EKA-T*
MAX9320ESA
MAX9320EUA*
MAX9320AEKA*
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 SOT23
8 SO-EP**
8 TSSOP
8 SOT23
*Future product—contact factory for availability.
**EP-Exposed pad.
TOP
MARK
—
—
—
AAIW
Pin Configurations
Q0 1
Q0 2
Q1 3
Q1 4
MAX9320
60kΩ
100kΩ
100kΩ
8 VCC
7D
6D
5 VEE
TSSOP*/SO
V_CC 1
V_EE 2
MAX9320A
V_CC
60kΩ
D3
100kΩ
100kΩ
D4
V_EE
SOT23*
8 Q0
7 Q0
6 Q1
5 Q1
V_CC 1
V_EE 2
D3
D4
MAX9320
V_CC
60kΩ
100kΩ
100kΩ
V_EE
SOT23*
8 Q0
7 Q0
6 Q1
5 Q1
________________________________________________________________ Maxim Integrated Products 1
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