MAX9310A Datasheet, PDF (1/11 Pages) Maxim Integrated Products – 1:5 Clock Driver with Selectable LVPECL Inputs/Single-Ended Inputs and LVDS Outputs

19-2542; Rev 0; 7/02
1:5 Clock Driver with Selectable LVPECL
Inputs/Single-Ended Inputs and LVDS Outputs
General Description
The MAX9310A is a fast, low-skew 1:5 differential driver
with selectable LVPECL inputs and LVDS outputs,
designed for clock distribution applications. This device
features an ultra-low propagation delay of 340ps with
48mA of supply current.
The MAX9310A operates from a 3V to 3.6V power sup-
ply for use in 3.3V systems. A 2:1 input multiplexer is
used to select one of two differential inputs. The input
selection is controlled through the CLKSEL pin.
This device features a synchronous enable function.
The MAX9310A LVPECL inputs can be driven by either
a differential or single-ended signal. A V_BB reference
voltage output is provided for use with single-ended
inputs. The device can also accept differential HSTL
signals.
The MAX9310A is offered in a space-saving 20-pin
TSSOP package and operates over the extended tem-
perature range from -40°C to +85°C.
Applications
Data and Clock Drivers and Buffers
Central-Office Backplane Clock Distribution
DSLAM
Base Stations
ATE
Features
o Guaranteed 1.0GHz Operating Frequency
o 8.0ps Output-to-Output Skew
o 340ps Propagation Delay
o Accepts LVPECL and Differential HSTL Inputs
o Synchronous Output Enable/Disable
o Two Selectable Differential Inputs
o 3V to 3.6V Supply Voltage
o On-Chip Reference for Single-Ended Operation
o ESD Protection: ±2kV (Human Body Model)
o Input Bias Resistors Drive Output Low for Open
Inputs
PART
MAX9310AEUP
Ordering Information
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
20 TSSOP
Functional Diagram appears at end of data sheet.
Typical Application Circuit
MAX9310A
Q_
Z_O = 50Ω
Z_O = 50Ω
Q_
RECEIVER
100Ω
Pin Configuration
TOP VIEW
Q0 1
QO 2
Q1 3
Q1 4
Q2 5
Q2 6
Q3 7
Q3 8
Q4 9
Q4 10
MAX9310A
20 V_CC
19 EN
18 V_CC
17 CLK1
16 CLK1
15 V_BB
14 CLK0
13 CLK0
12 CLKSEL
11 GND
TSSOP
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