MAX9232 Datasheet, PDF (1/1 Pages) Maxim Integrated Products – Programmable Spread-Spectrum and DC-Balance 21-Bit Deserializer

XX-XXXX; Rev 0; 9/05
Programmable Spread-Spectrum and
DC-Balance 21-Bit Deserializer
General Description
The MAX9232 deserializes three LVDS serial-data
inputs into 21 single-ended LVCMOS/LVTTL outputs. A
separate parallel-rate LVDS clock provides the timing
for deserialization. The MAX9232 features spread-spec-
trum capability, allowing the output data and clock
frequency to spread over a specified range to reduce
EMI. The single-ended data and clock outputs are pro-
grammable for a frequency spread of ±2%, ±4%, or no
spread. The spread-spectrum function is also available
when the MAX9232 operates in non-DC-balanced
mode. The modulation rate of the spread is 32kHz for a
33MHz LVDS clock input and scales linearly with fre-
quency. Using VSYNC on RxOUT13 and HSYNC on
RxOUT6, a reset of the spread-spectrum FIFO is per-
formed every frame, preventing FIFO overflow and
underflow. The single-ended outputs have a separate
supply, allowing +1.8V to +5V output logic levels.
The MAX9232 features programmable DC balance,
allowing isolation between a serializer and deserializer
using AC-coupling. The MAX9232 operates with the
MAX9209/MAX9213 serializer and has a falling-edge
strobe. The LVDS inputs meet ISO 10605 ESD specifi-
cations with ±25kV Air-Gap Discharge and ±8kV
Contact Discharge ratings.
The MAX9232 is available in a 48-pin TSSOP package and
operates within the -40°C to +85°C temperature range.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Ordering Information
PART
MAX9232EUM
TEMP RANGE PIN-PACKAGE
-40°C to +85°C 48 TSSOP
PKG
CODE
U48-1
Features
o Programmable ±4%, ±2%, or OFF Spread-Spectrum
Output for Reduced EMI
o Programmable DC Balance or Non-DC Balance
o DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
o Spread Spectrum Operates in DC-Balanced or Non-
DC-Balanced Mode
o FIFO Reset During Vertical Blanking
o 16MHz-to-34MHz (DC-Balanced) and 20MHz-to-
40MHz (Non-DC-Balanced) Operation
o High-Impedance Outputs when PWRDWN is Low
Allow Output Busing
o Fail-Safe Inputs in Non-DC-Balanced Mode
o Separate Output Supply Pins Allow Interface to
+1.8V, +2.5V, +3.3V, and +5V Logic
o LVDS Inputs Meet ISO 10605 ESD Protection at
±25kV Air Discharge and ±8kV Contact Discharge
o LVDS Inputs Meet IEC 61000-4-2 Level 4 ESD
Protection at ±15kV Air and ±8kV Contact Discharge
o LVDS Inputs Conform to ANSI TIA/EIA-644 Standard
o +3.3V Main Power Supply
Pin Configuration
TOP VIEW
RxOUT17 1
RxOUT18 2
GND 3
RxOUT19 4
RxOUT20 5
SSG 6
DCB 7
RxIN0- 8
RxIN0+ 9
RxIN1- 10
RxIN1+ 11
LVDSVCC 12
LVDSGND 13
RxIN2- 14
RxIN2+ 15
RxCLKIN- 16
RxCLKIN+ 17
LVDSGND 18
PLLGND 19
PLLVCC 20
PLLGND 21
PWRDWN 22
RxCLKOUT 23
RxOUT0 24
MAX9232
48 VCCO
47 RxOUT16
46 RxOUT15
45 RxOUT14
44 GND
43 RxOUT13
42 VCC
41 RxOUT12
40 RxOUT11
39 RxOUT10
38 GND
37 RxOUT9
36 VCCO
35 RxOUT8
34 RxOUT7
33 RxOUT6
32 GND
31 RxOUT5
30 RxOUT4
29 RxOUT3
28 VCCO
27 RxOUT2
26 RxOUT1
25 GND
TSSOP
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