MAX9174 Datasheet, PDF (1/14 Pages) Maxim Integrated Products – 670MHz LVDS-to-LVDS and Anything-to-LVDS 1:2 Splitters

19-2827; Rev 0; 4/03
670MHz LVDS-to-LVDS and Anything-to-LVDS
1:2 Splitters
General Description
The MAX9174/MAX9175 are 670MHz, low-jitter, low-
skew 1:2 splitters ideal for protection switching, loop-
back, and clock and signal distribution. The devices
feature ultra-low 1.0ps_(RMS) random jitter (max) that
ensures reliable operation in high-speed links that are
highly sensitive to timing errors.
The MAX9174 has a fail-safe LVDS input and LVDS out-
puts. The MAX9175 has an anything differential input
(CML/LVDS/LVPECL) and LVDS outputs. The outputs
can be put into high impedance using the power-down
inputs. The MAX9174 features a fail-safe circuit that dri-
ves the outputs high when the input is open, undriven
and shorted, or undriven and terminated. The MAX9175
has a bias circuit that forces the outputs high when the
input is open. The power-down inputs are compatible
with standard LVTTL/LVCMOS logic. The power-down
inputs tolerate undershoot of -1V and overshoot of V_CC
+ 1V. The MAX9174/MAX9175 are available in 10-pin
µMAX and 10-lead thin QFN with exposed pad pack-
ages, and operate from a single +3.3V supply over the
-40°C to +85°C temperature range.
Applications
Protection Switching
Loopback
Clock Distribution
Functional Diagram and Pin Configurations appear at end
of data sheet.
Features
o 1.0ps_(RMS) Jitter (max) at 670MHz
o 80ps_(P-P) Jitter (max) at 800Mbps Data Rate
o +3.3V Supply
o LVDS Fail-Safe Inputs (MAX9174)
o Anything Input (MAX9175) Accepts Differential
CML/LVDS/LVPECL
o Power-Down Inputs Tolerate -1.0V and V_CC + 1.0V
o Low-Power CMOS Design
o 10-Lead µMAX and Thin QFN Packages
o -40°C to +85°C Operating Temperature Range
o Conform to ANSI TIA/EIA-644 LVDS Standard
o IEC 61000-4-2 Level 4 ESD Rating
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX9174EUB
-40°C to +85°C 10 µMAX
MAX9174ETB*
-40°C to +85°C 10 Thin QFN-EP**
MAX9175EUB
-40°C to +85°C 10 µMAX
MAX9175ETB*
-40°C to +85°C 10 Thin QFN-EP**
*Future product—contact factory for availability.
**EP = Exposed paddle.
Typical Application Circuit
MAX9174
CLOCK DISTRIBUTION
ASIC
MAX9176
CLK IN
CLK1
MAX9174
CLK2
MAX9176
ASIC
CLK IN
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