MAX9160 Datasheet, PDF (1/13 Pages) Maxim Integrated Products – LVDS or LVTTL/LVCMOS Input to 14 LVTTL/LVCMOS Output Clock Driver

19-2392; Rev 0; 4/02
LVDS or LVTTL/LVCMOS Input to
14 LVTTL/LVCMOS Output Clock Driver
General Description
The MAX9160 125MHz, 14-port LVTTL/LVCMOS clock
driver repeats the selected LVDS or LVTTL/LVCMOS
input on two output banks. Each bank consists of seven
LVTTL/LVCMOS series terminated outputs and a bank
enable. The LVDS input has a fail-safe function. The
MAX9160 has a propagation delay that can be adjusted
using an external resistor to set the bias current for an
internal delay cell. The LVTTL/LVCMOS outputs feature
200ps maximum output-to-output skew and ±100ps maxi-
mum added peak-to-peak jitter.
The MAX9160 is designed to operate with a 3.3V sup-
ply voltage over the extended temperature range of
-40°C to +85°C. This device is available in 28-pin
exposed- and nonexposed-pad TSSOP and 32-lead
5mm x 5mm QFN packages.
Applications
Cellular Base Stations
Servers
Add/Drop Multiplexers
Digital Cross-Connects
DSLAMs
Networking Equipment
Typical Application Circuit and Functional Diagram appear
at end of data sheet.
Pin Configurations
TOP VIEW
OUTA5 1
OUTA6 2
ENA 3
SEL 4
SE_IN 5
V_CC 6
GND 7
IN+ 8
IN- 9
GND 10
RSET 11
ENB 12
OUTB0 13
OUTB1 14
MAX9160
28 OUTA4
27 OUTA3
26 GND
25 OUTA2
24 OUTA1
23 V_CC
22 OUTA0
21 OUTB6
20 GND
19 OUTB5
18 OUTB4
17 V_CC
16 OUTB3
15 OUTB2
TSSOP
Pin Configurations continued at end of data sheet.
Features
o LVDS or LVTTL/LVCMOS Input Selection
o LVDS Input Fail-Safe Sets Outputs High for Open,
Undriven Short, or Undriven Parallel Termination
o Two Output Banks with Separate Bank Enables
o Integrated Output Series Termination for 60Ω
Lines
o 200ps (max) Output-to-Output Skew
o ±100ps (max) Peak-to-Peak Added Output Jitter
o 42% to 58% Output Duty Cycle at 125MHz
o Guaranteed 125MHz Operating Frequency
o LVDS Input Is High Impedance with V_CC = 0V
or Open (Hot Swappable)
o 28-Pin Exposed- and Nonexposed-Pad TSSOP
or 32-Lead QFN Packages
o -40°C to +85°C Operating Temperature
o 3.0V to 3.6V Supply Voltage
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX9160EUI
-40°C to +85°C
28 TSSOP
MAX9160AEUI
-40°C to +85°C
28 TSSOP-EP**
MAX9160EGJ*
-40°C to +85°C
32 QFN-EP
*Future product—contact factory for availability.
**Exposed pad.
Function Table
EN_ SEL SE_IN
H
H
H
H
H
L or
open
H
L or
open
X
H
L or
open
X
V_ID
X
X
≥ +50mV
≤ -50mV
OUT_
H
L
H
L
H
L or
open
X
Open, undriven short, or
undriven parallel termination
H
L or
X
X
Open
V_ID = V_IN+ - V_IN-
H = high logic level
X
L
L = low logic level
X = don’t care
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