MAX5866 Datasheet, PDF (1/26 Pages) Maxim Integrated Products – Ultra-Low-Power, High-Dynamic- Performance, 60Msps Analog Front End

19-3223; Rev 0; 2/04
EVAALVUAAILTAIOBNLEKIT
Ultra-Low-Power, High-Dynamic-
Performance, 60Msps Analog Front End
General Description
The MAX5866 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless termi-
nals. The MAX5866 integrates dual, 8-bit receive ADCs
and dual, 10-bit transmit DACs while providing the high-
est dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
accept 1V_P-P full-scale signals. Typical I-Q channel
phase matching is ±0.2° and amplitude matching is
±0.05dB. The ADCs feature 48dB SINAD and 70.1dBc
spurious-free dynamic range (SFDR) at f_IN = 25MHz and
f_CLK = 60MHz. The DACs’ analog I-Q outputs are fully
differential with ±400mV full-scale output, and 1.4V com-
mon-mode level. Typical I-Q channel phase matching is
±0.4° and gain matching is ±0.1dB. The DACs also fea-
ture dual, 10-bit resolution with 64.2dBc SFDR, at f_OUT =
6MHz and f_CLK = 60MHz.
The ADCs and DACs operate simultaneously or indepen-
dently for frequency-division duplex (FDD) and time-divi-
sion duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of opera-
tion. The typical operating power is 96mW at f_CLK =
60MHz with the ADCs and DACs operating simultane-
ously in transceiver mode. The MAX5866 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5866 operates on a +2.7V to +3.3V ana-
log power supply and a +2.7V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
12mA in idle mode and 1µA in shutdown mode. The
MAX5866 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
Applications
Narrowband/Wideband CDMA Handsets
and PDAs
Fixed/Mobile Broadband Wireless Modems
3G Wireless Terminals
VSAT Modems
Pin Configuration appears at end of data sheet.
Features
♦ Integrated Dual, 8-Bit ADCs and Dual, 10-Bit DACs
♦ Ultra-Low Power
80mW at f_CLK = 60MHz (R_x Mode)
52.5mW at f_CLK = 60MHz (T_x Mode)
Low-Current Idle and Shutdown Modes
♦ Excellent Dynamic Performance
48dB SINAD at f_IN = 25MHz (ADC)
64.2dBc SFDR at f_OUT = 6MHz (DAC)
♦ Excellent Gain/Phase Match
±0.2° Phase, ±0.05dB Gain at f_IN = 25MHz (ADC)
♦ Internal/External Reference Option
♦ +2.7V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
♦ Multiplexed Parallel Digital Input/Output for
ADCs/DACs
♦ Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm)
♦ Evaluation Kit Available (Order MAX5865EVKIT)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX5866ETM
-40°C to +85°C
48 Thin QFN-EP*
(7mm x 7mm)
*EP = Exposed paddle.
Functional Diagram
IA+
IA-
QA+
QA-
ID+
ID-
QD+
QD-
REFP
COM
REFN
REFIN
MAX5866
ADC
ADC
OUTPUT
MUX
ADC
DAC
DAC
INPUT
MUX
DAC
SERIAL
REF
INTERFACE
AND AND SYSTEM
BIAS
CONTROL
DA0–DA7
CLK
DD0–DD9
DIN
SCLK
CS
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