MAX3892 Datasheet, PDF (1/11 Pages) Maxim Integrated Products – +3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1 Serializer with Clock Synthesis

19-2215; Rev 6; 10/07
EVAALVUAAILTAIOBNLEKIT
+3.3V, 2.5Gbps/2.7Gbps, SDH/SONET 4:1
Serializer with Clock Synthesis
General Description
The MAX3892 serializer is ideal for converting 4-bit-
wide, 622Mbps parallel data to 2.5Gbps serial data in
DWDM and SONET/SDH applications. A 4 ✕ 4-bit FIFO
allows for any static delay between the parallel output
clock and parallel input clock. Delay variation up to a
unit interval (UI) is allowed after reset. A fully integrated
phase-locked loop (PLL) synthesizes an internal
2.5GHz serial clock from a 622MHz, 155.5MHz,
77.8MHz, or 38.9MHz reference clock. A selectable
dual VCO allows excellent jitter performance at both
SONET and forward-error correction (FEC) data rates.
Operating from a single 3.3V supply, this device
accepts low-voltage differential-signal (LVDS) clock and
data inputs for interfacing with high-speed digital circuit-
ry, and delivers current-mode logic (CML) serial data
and clock outputs. A loopback data output is provided
to facilitate system diagnostic testing. The MAX3892 is
available in the extended temperature range (-40°C to
+85°C) in 44-pin QFN and TQFN packages.
Applications
SONET/SDH OC-48 Transmission Systems
WDM Transponders
Add/Drop Multiplexers
Dense Digital Cross-Connects
Backplane Interconnects
LVPECL
100Ω
VCCVCO
C_Z
Features
♦ Single +3.3V Supply
♦ 455mW Power Consumption
♦ 1.4ps_RMS Maximum Jitter Generation
♦ 4 ✕ 4-Bit FIFO Input Buffer
♦ 622Mbps/666Mbps Parallel to 2.5Gbps/2.7Gbps
Serial Conversion
♦ 622MHz/667MHz or 311MHz/333MHz Clock Input
♦ On-Chip Clock Synthesizer
♦ Multiple Clock Reference Frequencies:
(622.08MHz, 155.52MHz, 77.76MHz, 38.88MHz) or
(666.51MHz, 166.63MHz, 83.31MHz, 41.66MHz)
♦ LVDS Parallel Clock and Data Inputs
♦ CML Serial Data and Clock Outputs
♦ Additional CML Output for System Loopback
Testing
Ordering Information
PART
TEMP
RANGE
MAX3892EGH -40°C to +85°C
MAX3892ETH+ -40°C to +85°C
+Denotes a lead-free package.
PIN-
PACKAGE
44 QFN
44 TQFN
PKG
CODE
G4477-3
T4477-3
Typical Application Circuit
V_CC
SONET/SDH
FRAMER
RCLK- RCLK+ FIL VCCVCO CLKSET MODE RATESET
CML
LVDS
SDO+
PDI0+
SDO-
PDI0-
CML
SCLKO+
PDI3+
SCLKO-
PDI3-
SLBEN
MAX3892
SLBPD
TTL
MAX3273
LASER
DRIVER
LVDS
CML
PCLKI+
PCLKI-
SLBO+
SLBO-
MAX3882
1:4 DESERIALIZER
LVDS
OPTIONAL
WITH CDR
PCLKO+
FOR
PCLKO- _RESET
FIFOERROR
LOL
SYSTEM
LOOPBACK
TEST
THIS SYMBOL REPRESENTS A TRANSMISSION
LINE OF CHARACTERISTIC IMPEDANCE Z_O = 50Ω.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.