MAX3880 Datasheet, PDF (1/12 Pages) Maxim Integrated Products – +3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery

19-1467; Rev 1; 12/99
+3.3V, 2.488Gbps, SDH/SONET
1:16 Deserializer with Clock Recovery
General Description
The MAX3880 deserializer with clock recovery is ideal
for converting 2.488Gbps serial data to 16-bit-wide,
155Mbps parallel data for SDH/SONET applications.
Operating from a single +3.3V supply, this device
accepts high-speed serial-data inputs and delivers low-
voltage differential-signal (LVDS) parallel clock and
data outputs for interfacing with digital circuitry.
The MAX3880 includes a low-power clock recovery and
data retiming function for 2.488Gbps applications. The
fully integrated phase-locked loop (PLL) recovers a
synchronous clock signal from the serial NRZ data
input; the signal is then retimed by the recovered clock.
The MAX3880’s jitter performance exceeds all
SDH/SONET specifications. An additional 2.488Gbps
serial input is available for system loopback diagnostic
testing. The device also includes a TTL-compatible
loss-of-lock (LOL) monitor and LVDS synchronization
inputs that enable data realignment and reframing.
The MAX3880 is available in the extended temperature
range (-40°C to +85°C) in a 64-pin TQFP-EP (exposed
pad) package.
Applications
2.488Gbps SDH/SONET Transmission Systems
Add/Drop Multiplexers
Digital Cross-Connects
Features
o Single +3.3V Supply
o 910mW Operating Power
o Fully Integrated Clock Recovery and Data
Retiming
o Exceeds ANSI, ITU, and Bellcore Specifications
o Additional High-Speed Input Facilitates System
Loopback Diagnostic Testing
o 2.488Gbps Serial to 155Mbps Parallel Conversion
o LVDS Data Outputs and Synchronization Inputs
o Tolerates >2000 Consecutive Identical Digits
o Loss-of-Lock Indicator
PART
MAX3880ECB
*Exposed pad
Ordering Information
TEMP. RANGE
-40°C to +85°C
PIN-PACKAGE
64 TQFP-EP*
Pin Configuration appears at end of data sheet.
Typical Application Circuit
+3.3V
0.01µF
+3.3V
V_CC
FIL
OUT+
IN+ MAX3866
PRE/POSTAMPLIFIER
OUT-
LOP
TTL
PHADJ+ PHADJ-
V_CC
SDI+
SDI-
SLBI-
SLBI+
MAX3880
PD15+
PD15-
100Ω*
PD0+
100Ω*
PD0-
PCLK+
100Ω*
PCLK-
SYNC+
SIS FIL+
FIL-
GND
SYSTEM
LOOPBACK
C_F
TTL
1µF
LOL ^SYNC-
TTL
*REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.
THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z₀ = 50Ω.
V_CC
OVERHEAD
TERMINATION
________________________________________________________________ Maxim Integrated Products 1
For free samples and the latest literature, visit www.maxim-ic.com or phone [phone].
For small orders, phone [phone].