MAX3877 Datasheet, PDF (1/16 Pages) Maxim Integrated Products – 2.5Gbps, +3.3V Clock and Data Retiming ICs with Vertical Threshold Adjust

19-2062; Rev 0; 5/01
2.5Gbps, +3.3V Clock and Data Retiming ICs
with Vertical Threshold Adjust
General Description
The MAX3877/MAX3878 are compact, low-power clock
recovery and data retiming ICs for 2.488Gbps SONET/
SDH applications. The fully integrated phase-locked
loop (PLL) recovers a synchronous clock signal from
the serial NRZ data input, which is retimed by the
recovered clock. An additional 2.488Gbps serial input
is available for system loopback diagnostic testing, or
this input can be connected to a 155MHz reference
clock to maintain a valid clock output in the absence of
data transitions. The MAX3877/MAX3878 provide verti-
cal threshold and phase-adjust control to optimize sys-
tem BER in DWDM applications.
These devices provide both loss-of-lock (LOL) and
loss-of-signal (LOS) monitors. Differential CML outputs
are provided for both clock and data signals on the
MAX3877, and differential PECL outputs are provided
for clock and data signals on the MAX3878.
The MAX3877/MAX3878 are designed for both section-
regenerator and terminal-receiver applications in OC-
48/STM-16 transmission systems. Their jitter performance
exceeds all of the SONET/SDH specifications. These
devices operate from a single +3.0V to +3.6V supply over
a -40°C to +85°C temperature range. Typical power con-
sumption is only 540mW with a +3.3V supply (MAX3878).
They are available in a 32-pin TQFP-EP package with an
exposed pad, as well as in die form.
Applications
Long Haul and Metro Systems with
Optical Amplification
DWDM Transmission Systems
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
Typical Operating Circuit appears at end of data sheet.
Features
o Exceeds ANSI, ITU, and Bellcore SONET/SDH
Specifications
o Adjustable Input Threshold (±180mV)
o 10mVp-p to 1.2Vp-p Differential Input Range
o 540mW Power Dissipation (at +3.3V)
o Fully Integrated Clock Recovery and Data
Retiming
o Optional Holdover Capability (Using External
Reference Clock)
o 0.003UI_RMS Clock Jitter Generation
o Tolerates >2000 Consecutive Identical Digits
o Additional 2.488Gbps Input for Diagnostic
Loopback Testing
o Differential PECL or CML Data and Clock Outputs
o Loss-of-Signal Indicator
o Loss-of-Lock Indicator
Ordering Information
PART
TEMP. RANGE PIN-PACKAGE
MAX3877EHJ
-40°C to +85°C 32 TQFP-EP*
MAX3877E/D*** -40°C to +85°C DICE**
MAX3878EHJ
-40°C to +85°C 32 TQFP-EP*
MAX3878E/D*** -40°C to +85°C DICE**
* Exposed pad
** Dice are designed to operate over this range, but are tested
and guaranteed at T_A = +25°C only. contact factory for avail-
ability.
*** Future product—contact factory for availability.
Pin Configuration
TOP VIEW
GND 1
THADJ 2
VCC 3
SDI- 4
SDI+ 5
VCC 6
SIS 7
LREF 8
32 31 30 29 28 27 26 25
MAX3877
MAX3878
24 VCC
23 SDO+
22 SDO-
21 VCC
20 VCC
19 SCLKO+
18 SCLKO-
17 VCC
9 10 11 12 13 14 15 16
TQFP
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