MAX3872 Datasheet, PDF (1/13 Pages) Maxim Integrated Products – Multirate Clock and Data Recovery with Limiting Amplifier

19-2709; Rev 1; 5/03
EVAALVUAAILTAIOBNLEKIT
Multirate Clock and Data Recovery
with Limiting Amplifier
General Description
The MAX3872 is a compact, multirate clock and data
recovery with limiting amplifier for OC-3, OC-12, OC-24,
OC-48, OC-48 with FEC SONET/SDH and Gigabit
Ethernet (1.25Gbps/2.5Gbps) applications. Without using
an external reference clock, the fully integrated phase-
locked loop (PLL) recovers a synchronous clock signal
from the serial NRZ data input. The input data is then
retimed by the recovered clock, providing a clean data
output. An additional serial input (SLBI±) is available for
system loopback diagnostic testing. Alternatively, this
input can be connected to a reference clock to maintain a
valid clock output in the absence of data transitions. The
device also includes a loss-of-lock (LOL) output.
The MAX3872 contains a vertical threshold control to
compensate for optical noise due to EDFAs in DWDM
transmission systems. The recovered data and clock
outputs are CML with on-chip 50Ω back termination on
each line. Its jitter performance exceeds all
SONET/SDH specifications.
The MAX3872 operates from a single +3.3V supply and
typically consumes 580mW. It is available in a 5mm x
5mm 32-pin thin QFN with exposed-pad package and
operates over a -40°C to +85°C temperature range.
Applications
SONET/SDH Receivers and Regenerators
Add/Drop Multiplexers
Digital Cross-Connects
SONET/SDH Test Equipment
DWDM Transmission Systems
Access Networks
Pin Configuration appears at end of data sheet.
Features
o Multirate Data Input: 2.667Gbps (FEC), 2.488Gbps,
1.244Gbps, 622.08Mbps, 155.52Mbps,
1.25Gbps/2.5Gbps (Ethernet)
o Reference Clock Not Required for Data
Acquisition
o Exceeds ANSI, ITU, and Bellcore SONET/SDH
Jitter Specifications
o 2.7mUI_RMS Jitter Generation
o 10mV_P-P Input Sensitivity Without Threshold
Adjust
o 0.65UI_P-P High-Frequency Jitter Tolerance
o ±170mV Input Threshold Adjust Range
o Clock Holdover Capability Using Frequency-
Selectable Reference Clock
o Serial Loopback Input Available for System
Diagnostic Testing
o Loss-of-Lock (LOL) Indicator
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX3872EGJ -40°C to +85°C 32 QFN
PKG
CODE
G3255-1
Typical Application Circuit
+3.3V
VCC
FILTER
OUT+
CFIL
0.82µF
+3.3V
CAZ
0.1µF
+3.3V +3.3V
FIL VCC_VCO CAZ- CAZ+ FREFSET VCC
SDI+
MAX3745*
OUT-
IN
GND
+3.3V
SDI-
SLBI+
SLBI-
MAX3872
SDO+
CML
SDO-
SCLKO+
CML
SCLKO-
VCTRL
*FUTURE PRODUCT
SYSTEM
LOOPBACK DATA
VREF
SIS LREF LOL RS1 RS2 RATESET GND
+3.3V
________________________________________________________________ Maxim Integrated Products 1
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