MAX3620 Datasheet, PDF (1/6 Pages) Maxim Integrated Products – Delay Lines for High-Speed Clock Distribution Systems

19-3550; Rev 0; 1/05
Delay Lines for High-Speed Clock
Distribution Systems
General Description
The MAX3620 series is a family of high-performance
passive delay lines for use in QDR/QDRII synchronous
memory systems. These delay lines support high-speed
transceiver logic (HSTL) source terminated transmission
with an unterminated load at the receiver, and deliver
accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns
for the generation of the quarter clock phase. The
MAX3620 is offered in a small 3mm x 3mm package
which contains two delay lines of equal length that can
be driven either differentially or single-endedly.
Applications
QDR/QDRII Memory Systems
Multiphase Clock Generation
TOP VIEW
Pin Configuration
Features
♦ Supports HSTL Source Terminated Lines
♦ All-Passive Design
♦ Compatible with 100Ω Differential and 50Ω Single-
Ended Transmission Lines
♦ Small 3mm x 3mm Package
PART
MAX3620AETT
MAX3620BETT
MAX3620CETT
MAX3620DETT
Ordering Information
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
6 TDFN
6 TDFN
6 TDFN
6 TDFN
IN1 1
COMMON 2
IN2 3
MAX3620
*EP
TDFN
*EP—EXPOSED PAD. MUST BE CONNECTED TO THE
SAME POTENTIAL AS COMMON.
6 OUT1
5 COMMON
4 OUT2
PART
MAX3620AETT
MAX3620BETT
MAX3620CETT
MAX3620DETT
Selector Guide
PKG CODE
T633-2
T633-2
T633-2
T633-2
TOP MARK
AJX
AIY
AIZ
AJA
Typical Application Circuit
QDR II SRAM CLOCK OUTPUT
HSTL SOURCE TERMINATED
50Ω
50Ω
DELAY LINE
1/4 CLOCK PERIOD
IN1
OUT1
50Ω
COMMON
MAX3620
COMMON
50Ω
IN2
OUT2
QDR II SRAM CLOCK INPUT
HSTL HIGH-Z CMOS
90° PHASE
270° PHASE
50Ω
180° PHASE
50Ω
50Ω
0° PHASE
50Ω
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