MAX19586 Datasheet, PDF (1/20 Pages) Maxim Integrated Products – High-Dynamic-Range, 16-Bit, 80Msps ADC with -82dBFS Noise Floor

19-3758; Rev 0; 8/05
EVAALVUAAILTAIOBNLEKIT
High-Dynamic-Range, 16-Bit,
80Msps ADC with -82dBFS Noise Floor
General Description
The MAX19586 is a 3.3V, high-speed, high-perfor-
mance analog-to-digital converter (ADC) featuring a
fully differential wideband track-and-hold (T/H) and a
16-bit converter core. The MAX19586 is optimized for
multichannel, multimode receivers, which require the
ADC to meet very stringent dynamic performance
requirements. With a -82dBFS noise floor, the
MAX19586 allows for the design of receivers with supe-
rior sensitivity requirements.
At 80Msps, the MAX19586 achieves a 79.2dB signal-to-
noise ratio (SNR) and an 84.3dBc/100dBc single-tone
spurious-free dynamic range (SFDR) performance
(SFDR1/SFDR2) at f_IN = 70MHz. The MAX19586 is not
only optimized for excellent dynamic performance in
the 2nd Nyquist region, but also for high-IF input fre-
quencies. For instance, at 130MHz, the MAX19586
achieves an 82.5dBc SFDR and its SNR performance
stays flat (within 2.5dB) throughout the 4th Nyquist
region. This level of performance makes the part ideal
for high-performance digital receivers.
The MAX19586 operates from a 3.3V analog supply
voltage and a 1.8V digital voltage, features a 2.56V_P-P
full-scale input range, and allows for a guaranteed sam-
pling speed of up to 80Msps. The input track-and-hold
stage operates with a 600MHz full-scale, full-power
bandwidth.
The MAX19586 features parallel, low-voltage CMOS-
compatible outputs in two’s-complement output format.
The MAX19586 is manufactured in an 8mm x 8mm,
56-pin thin QFN package with exposed paddle (EP) for
low thermal resistance, and is specified for the extend-
ed industrial (-40°C to +85°C) temperature range.
Applications
Cellular Base-Station Transceiver Systems (BTS)
Wireless Local Loop (WLL)
Multicarrier Receivers
Multistandard Receivers
E911 Location Receivers
High-Performance Instrumentation
Antenna Array Processing
Features
o 80Msps Minimum Sampling Rate
o -82dBFS Noise Floor
o Excellent Dynamic Performance
80dB/79.2dB SNR at f_IN = 10MHz/70MHz
and -2dBFS
96dBc/102dBc Single-Tone SFDR1/
SFDR2 at f_IN = 10MHz
84.3dBc/100dBc Single-Tone SFDR1/
SFDR2 at f_IN = 70MHz
o Less than 0.1ps Sampling Jitter
o 1.1W Power Dissipation
o 2.56V_P-P Fully Differential Analog Input Voltage
Range
o CMOS-Compatible Two’s-Complement Data
Output
o Separate Data Valid Clock and Over-Range
Outputs
o Flexible Input Clock Buffer
o 3.3V Analog Power Supply; 1.8V Digital Output
Supply
o Small 8mm x 8mm x 0.8mm 56-Pin Thin QFN
Package
o EV Kit Available for MAX19586
(Order MAX19586EVKIT)
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
PKG
CODE
MAX19586ETN -40°C to +85°C 56 Thin QFN-EP T5688-2
MAX19586ETN+ -40°C to +85°C 56 Thin QFN-EP T5688-2
+Denotes lead-free package.
Pin Configuration
TOP VIEW
42 41 40 39 38 37 36 35 34 33 32 31 30 29
D9 43
28 AGND
D10 44
27 REFIN
D11 45
26 REFOUT
D12 46
D13 47
D14 48
D15 49
DAV 50
MAX19586
25 AVDD
24 AVDD
23 AVDD
22 AGND
21 AGND
DVDD 51
DGND 52
DOR 53
N.C. 54
AVDD 55
AVDD 56
20 AGND
19 AVDD
18 AVDD
17 AVDD
16 N.C.
15 N.C.
1 2 3 4 5 6 7 8 9 10 11 12 13 14
THIN QFN
8mm x 8mm
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