MAX19541 Datasheet, PDF (1/23 Pages) Maxim Integrated Products – 12-Bit, 125Msps ADC with CMOS Outputs for Wideband Applications

19-3432; Rev 0; 11/04
EVAALVUAAILTAIOBNLEKIT
12-Bit, 125Msps ADC with CMOS
Outputs for Wideband Applications
General Description
The MAX19541 monolithic 12-bit, 125Msps analog-to-
digital converter (ADC) is optimized for outstanding
dynamic performance at high-IF frequencies of
300MHz and beyond. This device operates with con-
version rates up to 125Msps while consuming only
861mW.
At 125Msps and an input frequency of 240MHz, the
MAX19541 achieves a spurious-free dynamic range
(SFDR) of 71.5dBc. The MAX19541 features an excel-
lent signal-to-noise ratio (SNR) of 65.4dB at 10MHz that
remains flat (within 3dB) for input tones up to 250MHz.
This makes the MAX19541 ideal for wideband applica-
tions such as power-amplifier predistortion in cellular
base-station transceiver systems.
The MAX19541 operates in either parallel mode where
the data outputs appear on a single parallel port at the
sampling rate, or in demux parallel mode, where the out-
puts appear on two separate parallel ports at one-half
the sampling rate. See the Mode of Operation section.
The MAX19541 operates on a single 1.8V supply. The
analog input is differential and can be AC- or DC-cou-
pled. The ADC also features a selectable on-chip
divide-by-2 clock circuit that allows clock frequencies
as high as 250MHz. This helps to reduce the phase
noise of the input clock source, allowing for higher
dynamic performance. For best performance, a differ-
ential LVPECL sampling clock is recommended. The
digital outputs are CMOS compatible and the data for-
mat can be selected to be either two’s complement or
offset binary.
A pin-compatible, 12-bit, 170Msps version of the
MAX19541 is also available. Refer to the MAX19542
data sheet for more information.
The MAX19541 is available in a 68-pin QFN with
exposed paddle (EP) and is specified over the extend-
ed (-40°C to +85°C) temperature range.
Applications
Base-Station Power Amplifier Linearization
Cable Head-End Receivers
Wireless and Wired Broadband Communication
Communications Test Equipment
Radar and Satellite Subsystems
Features
♦ 125Msps Conversion Rate
♦ SNR = 65dB, f_IN = 100MHz at 125Msps
♦ SFDR = 77dBc, f_IN = 100MHz at 125Msps
♦ ±0.7 LSB INL, ±0.25 DNL (typ)
♦ 861mW Power Dissipation at 125Msps
♦ On-Chip Selectable Divide-by-2 Clock Input
♦ Parallel or Demux Parallel Digital CMOS Outputs
♦ Reset Option for Synchronizing Multiple ADCs
♦ Data Clock Output
♦ Offset Binary or Two’s-Complement Output
♦ Evaluation Kit Available (MAX19541EVKIT)
Ordering Information
PART
TEMP RANGE
MAX19541EGK -40°C to +85°C
EP = Exposed paddle.
PIN-
PACKAGE
68 QFN-EP*
PKG
CODE
G6800-4
Pin Configuration
TOP VIEW
68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
AVCC 1
AGND 2
REFIO 3
REFADJ 4
AGND 5
AVCC 6
AGND 7
INP 8
INN 9
AGND 10
AVCC 11
AVCC 12
AVCC 13
AVCC 14
RESET 15
DEMUX 16
CLKDIV 17
MAX19541
51 DA4
50 DA3
49 DA2
48 DA1
47 DA0
46 ORB
45 OGND
44 OVCC
43 DCLKP
42 DCLKN
41 OVCC
40 DB11
39 DB10
38 DB9
37 DB8
36 DB7
35 DB6
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
NOTE: EXPOSED PADDLE CONNECTED TO AGND. _QFN
________________________________________________________________ Maxim Integrated Products 1
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