DS26102 Datasheet, PDF (1/64 Pages) Maxim Integrated Products – 16-Port TDM-to-ATM PHY

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GENERAL DESCRIPTION
On the transmit side, the DS26102 receives ATM cells
from an ATM device through a UTOPIA II interface,
provides cell buffering (up to 4 cells), HEC generation
and insertion, cell scrambling, and converts the data
to a serial stream appropriate for interfacing to a
T1/E1 framer or transceiver. On the receive side, the
DS26102 receives a TDM stream from a T1/E1 framer
or transceiver; searches for the cell alignment; verifies
the HEC; provides cell filtering, descrambling, and cell
buffering; and passes the cells to an ATM device
through the UTOPIA II interface. Other low-level traffic
management functions are selectable for the transmit
and receive paths. The DS26102 can also be used in
fractional T1/E1 applications.
The DS26102 maps ATM cells to T1/E1 TDM frames
as per the ATM Forum Specifications af-phy-0016.000
and af-phy-0064.000. In the receive direction, the cell
delineation mechanism used for finding ATM cell
boundary within T1/E1 frame is performed as per ITU
I.432. The DS26102 provides a mapping solution for
up to 16 T1/E1 TDM ports. The terms physical layer
(PHY) and line side are used synonymously in this
document and refer to the device interfacing with the
line side of the DS26102. The terms ATM layer and
system side are used synonymously and refer to the
DS26102’s UTOPIA II interface.
FUNCTIONAL DIAGRAM
16 TDM
PORTS
DS26102 UTOPIA II
DS26102
16-Port TDM-to-ATM PHY
FEATURES
§ Supports 16 T1/E1 TDM Ports
§ Supports Fractional T1/E1
§ Compliant to ATM Forum Specifications for ATM
Over T1 and E1
§ Standard UTOPIA II Interface to the ATM Layer
§ Configurable UTOPIA Address Range
§ Configurable Tx FIFO Depth to 2, 3, or 4 Cells
§ Optional Payload Scrambling in Transmit
Direction and Descrambling in Receive Direction
per ITU I.432
§ Optional HEC Insertion in Transmit Direction with
Programmable COSET Polynomial Addition
§ HEC-Based Cell Delineation
§ Single-Bit HEC Error Correction in the Receive
Direction
§ Receive HEC-Errored Cell Filtering
§ Receive Idle/Unassigned Cell Filtering
§ User-Definable Cell Filtering
§ 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor
Interface
§ Internal Clock Generator Eliminates External
High-Speed Clocks
§ Internal One-Second Timer
§ Detects/Reports Up to Eight External Status
Signals with Interrupt Support
§ IEEE 1149.1 JTAG Boundary Scan Support
§ 17mm x 17mm, 256-Pin CSBGA
Features continued on page 5.
APPLICATIONS
DSLAMS
ATM Over T1/E1
Routers
IMA
ORDERING INFORMATION
PART
DS26102
TEMP RANGE
-40°C to +85°C
PIN-PACKAGE
256 CSBGA
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
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REV: 021403