DS26101 Datasheet, PDF (1/62 Pages) Maxim Integrated Products – 8-Port TDM-to-ATM PHY

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GENERAL DESCRIPTION
On the transmit side, the DS26101 receives ATM cells
from an ATM device through a UTOPIA II interface,
provides cell buffering (up to 4 cells), HEC generation
and insertion, cell scrambling, and converts the data
to a serial stream appropriate for interfacing to a
T1/E1 framer or transceiver. On the receive side, the
DS26101 receives a TDM stream from a T1/E1 framer
or transceiver; searches for the cell alignment; verifies
the HEC; provides cell filtering, descrambling, and cell
buffering; and passes the cells to an ATM device
through the UTOPIA II interface. Other low-level traffic
management functions are selectable for the transmit
and receive paths. The DS26101 can also be used in
fractional T1/E1 applications.
The DS26101 maps ATM cells to T1/E1 TDM frames
as specified in ATM Forum Specifications af-phy-
0016.000 and af-phy-0064.000. In the receive
direction, the cell delineation mechanism used for
finding ATM cell boundary within T1/E1 frame is
performed as per ITU I.432. The DS26101 provides a
mapping solution for up to 8 T1/E1 TDM ports. The
terms physical layer (PHY) and line side are used
synonymously in this document and refer to the
device interfacing with the line side of the DS26101.
The terms ATM layer and system side are used
synonymously and refer to the DS26101’s UTOPIA II
interface.
FUNCTIONAL DIAGRAM
8 TDM
PORTS
Dallas
Semiconductor
DS26101
UTOPIA II
DS26101
8-Port TDM-to-ATM PHY
FEATURES
§ Supports 8 T1/E1 TDM Ports
§ Supports Fractional T1/E1
§ Compliant to ATM Forum Specifications for ATM
Over T1 and E1
§ Standard UTOPIA II Interface to the ATM Layer
§ Configurable UTOPIA Address Range
§ Configurable Tx FIFO Depth to 2, 3, or 4 Cells
§ Optional Payload Scrambling in Transmit
Direction and Descrambling in Receive Direction
per ITU I.432
§ Optional HEC Insertion in Transmit Direction with
Programmable COSET Polynomial Addition
§ HEC-Based Cell Delineation
§ Single-Bit HEC Error Correction in the Receive
Direction
§ Receive HEC-Errored Cell Filtering
§ Receive Idle/Unassigned Cell Filtering
§ User-Definable Cell Filtering
§ 8-Bit Mux/Nonmux, Motorola/Intel Microprocessor
Interface
§ Internal Clock Generator Eliminates External
High-Speed Clocks
§ Internal One-Second Timer
§ Detects/Reports Up to Eight External Status
Signals with Interrupt Support
§ IEEE 1149.1 JTAG Boundary Scan Support
§ 17mm x 17mm, 256-pin CSBGA
APPLICATIONS
DSLAMS
ATM Over T1/E1
Routers
IMA
ORDERING INFORMATION
PART
DS26101
TEMP RANGE PIN-PACKAGE
-40°C to +85°C 256 CSBGA
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