CY7C1010DV33_08 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 2-Mbit (256K x 8) Static RAM

CY7C1010DV33
2-Mbit (256K x 8) Static RAM
Features
■ Pin and function compatible with CY7C1010CV33
■ High speed
❐ t_AA = 10 ns
■ Low active power
❐ I_CC = 90 mA at 10 ns
■ Low CMOS standby power
❐ I_SB2 = 10 mA
■ 2.0V data retention
■ Automatic power down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE and OE features
■ Available in Pb-Free 36-pin SOJ and 44-pin TSOP II packages
Functional Description
The CY7C1010DV33 is a high performance CMOS Static RAM
organized as 256K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE), an active LOW
Output Enable (OE), and three-state drivers. Writing to the
device is accomplished by taking Chip Enable (CE) and Write
Enable (WE) inputs LOW. Data on the eight I/O pins (I/O₀
through I/O₇) is then written into the location specified on the
address pins (A₀ through A₁₇).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O pins.
The eight input and output pins (I/O₀ through I/O₇) are placed in
a high impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1010DV33 is available in 36-pin SOJ and 44-pin
TSOP II packages with center power and ground (revolutionary)
pinout.
Refer to the Cypress application note AN1064, SRAM System
Guidelines for best practice recommendations.
Logic Block Diagram
INPUT BUFFER
IO0
A0
A1
IO1
A2
A3
IO2
A4
A5
256K x 8
IO3
A6
A7
ARRAY
IO4
A8
A9
IO5
A10
IO6
CE
WE
COLUMN DECODER
POWER
DOWN
IO7
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00062 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 6, 2008
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